Frequency multiplier circuit operable with an external reference

Details Frequency multiplier circuit operable with an external reference Frequency multiplier circuit operable with an external reference

1998-11-25

2000-11-14

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, 327158, H03B 1900

Patent

active

061475254

ABSTRACT:
A frequency multiplier circuit needs to have a voltage controlled oscillator circuit having a wide oscillation frequency range, or delay cells each having a delay value which can be controlled over a wide range. Depending on the frequency multiplication factor, however, a frequency multiplied clock signal susceptible to influence of noise is generated. In the disclosed frequency multiplier circuit, there are provided a phase comparison input selection circuit for conducting a selection out of output signals of delay cells forming a voltage controlled delay circuit according to a frequency multiplication factor setting signal and an input frequency range setting signal and outputting the selected signal to a phase comparator, and a selected waveform generation circuit for generating a frequency multiplied clock signal CKOUT from the output signals of the delay cells according to the frequency multiplication factor setting signal and the input frequency range setting signal.

REFERENCES:
patent: 5355037 (1994-10-01), Andresen et al.
patent: 5389830 (1995-02-01), Buckingham et al.
patent: 5451911 (1995-09-01), Colvin et al.
patent: 5955902 (1999-09-01), Takada et al.
A. Rothermel, et al., IEEE Journal of Solid-State Circuits, vol. 28, No. 7, pp. 853-856, "Analog Phase Measuring Circuit for Digital CMOS IC's", Jul., 1993.
A. Efendovich, et al., IEEE Journal of solid-state circuits, vol. 29, No. 1, pp. 67-70, "Multifrequency Zero-Jitter Delay-Locked Loop", Jan., 1994.

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