Frequency multiplier circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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327116, 327284, 377 47, H03B 1900

Patent

active

055303870

ABSTRACT:
A frequency multiplier circuit comprising a first delay circuit for delaying sequentially a reference clock signal, a frequency doubler for delaying the reference clock signal and combining logically the delayed reference clock signal and the reference clock signal, a second delay circuit for delaying sequentially an output signal from the frequency doubler, a signal detector for logically combining the output signal from the frequency doubler and a plurality of output signals from the second delay circuit to detect a desired duty factor of signal, a decoder for decoding a plurality of output signals from the first delay circuit and a plurality of output signals from the signal detector to output a signal delayed by n times half a period of the reference clock signal, and a frequency generator for logically combining an output signal from the decoder and the reference clock signal to generate a multiple frequency of that of the reference clock signal. According to the present invention, the frequency multiplier circuit can automatically adjust an operating point regardless of a variation in a temperature or a process parameter.

REFERENCES:
patent: 4596954 (1986-06-01), Haque
patent: 4707665 (1987-11-01), Nugent et al.
patent: 4799022 (1989-01-01), Skierszkan
patent: 5077686 (1991-12-01), Rubinstein
patent: 5111066 (1992-05-01), Artieri et al.
patent: 5321734 (1994-06-01), Ogata
patent: 5365181 (1994-11-01), Mair

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