Frequency multiplier and semiconductor integrated circuit employ

Details Frequency multiplier and semiconductor integrated circuit employ Frequency multiplier and semiconductor integrated circuit employ

1996-07-22

1998-02-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

377 47, H03B 1900

Patent

active

057215014

ABSTRACT:
A frequency multiplier has a delay circuit consisting of delay units each having a delay time and being connected in series to sequentially delay an input clock signal, a pulse width detector for measuring and storing the width of a pulse of the input clock signal according to the outputs of the delay units, a first selector for selecting one of the outputs of the delay units according to the output of the pulse width detector, a second selector for selecting one of the inverted outputs of the delay units according to the output of the pulse width detector, and first and second output flip-flops. The first and second output flip-flops are reset according to the outputs of the first and second selectors and are set in response to rising and falling edges of the input clock signal, to generate a frequency-multiplied clock signal.

REFERENCES:
patent: 4777448 (1988-10-01), Satoh
patent: 4799022 (1989-01-01), Skierszkan
patent: 5057784 (1991-10-01), Park
patent: 5321743 (1994-06-01), Ogata
patent: 5530387 (1996-06-01), Kim
patent: 5548235 (1996-08-01), Marbot
patent: 5614841 (1997-03-01), Marbot et al.

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