Frequency multiplier

Details Frequency multiplier Frequency multiplier

2007-06-05

2007-06-05

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S116000

Reexamination Certificate

active

11298591

ABSTRACT:
A multiplier core outputs a single-phase signal containing a frequency component having a frequency which is an even multiple of the frequency of an input signal. A differential amplifier includes first and second nMOS transistors having respective source terminals connected to each other. The output signal from the multiplier core is inputted to the gate terminal of the first nMOS transistor, and the gate terminal of the second nMOS transistor is AC grounded. The differential amplifier differentially amplifies the signals inputted to the gate terminals of the first and second nMOS transistors to output a potential at the drain terminals of the first and second nMOS transistors as a differential signal. The output terminal of the multiplier core is connected through a series LC circuit to the source terminals of the first and second nMOS transistors.

REFERENCES:
patent: 5815014 (1998-09-01), Zhang et al.
patent: 6100731 (2000-08-01), Otaka
patent: 6882191 (2005-04-01), Kwok
patent: 2006/0145737 (2006-07-01), Yamamoto et al.
patent: 7-135424 (1995-05-01), None
patent: 2003-229722 (2003-08-01), None
patent: 2003-283251 (2003-10-01), None
Yamamoto et al. “1.2/2.4GHz, 2.6/5.2-GHz-Band CMOS Frequency Doublers for Wireless Applications,” Technical Report of the Institute of Electronics, Information and Communication Engineers, ED2003-210, pp. 25-30. JAPAN, no date.

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