Frequency multiplier

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S119000, C377S047000

Reexamination Certificate

active

07830184

ABSTRACT:
A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

REFERENCES:
patent: 6353648 (2002-03-01), Suzuki
patent: 2005/0174911 (2005-08-01), Shutoku et al.
patent: 99-0044993 (1999-06-01), None
patent: 1999-0044993 (1999-06-01), None
patent: WO 2004/042721 (2004-05-01), None
International Preliminary Report on Patentability dated Jan. 9, 2007, for corresponding International Application No. PCT/KR2005/002434, listing the cited reference and WO 04/042721 A1 previously cited in an IDS on Jan. 30, 2007.
International Search Report, dated Nov. 7, 2005, corresponding to PCT/KR2005/002434.

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