Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
1999-09-09
2001-03-06
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S122000, C327S119000
Reexamination Certificate
active
06198317
ABSTRACT:
RELATED APPLICATION
This invention is related to U.S. patent application Ser. No. 09/026,842, entitled “Duty Cycle Control Buffer Circuit with Selective Frequency Dividing Function”, filed on Feb. 20, 1998 for Hwang-Cherng Chow et al. The contents of the above-noted application is incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to CMOS integrated circuits. More particularly, it relates to a frequency multiplication circuit which makes use of duty cycle control buffers.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) circuits are well known and are often used for frequency multiplication purposes. The main components of a PLL circuit, as shown in
FIG. 1
, comprise a phase detector/comparator, a loop filter (LPF), and a voltage-controlled oscillator (VCO). Typically, a PLL circuit is designed to generate an output clock signal at twice the frequency (2f) of an input clock signal (f). However, it is also generally desirable for a clock signal to have a 50% duty cycle (symmetrical square wave). In order to ensure a 50 percent duty cycle for the output clock signal (2f) in the PLL circuit of
FIG. 1
, the VCO is operated at 4 times f, and a divide-by-2 counter is used to provide the 2f output at a 50% duty cycle. In addition, a divide-by-4 counter is needed in the feedback loop to provide a correct frequency comparison with the input clock f in the phase detector. While this PLL design approach offers flexibility for frequency multiplication, it does have at least two significant disadvantages:
(1) increased power consumption due to the VCO operation at 4X frequency; and
(2) complex analog design of the VCO circuit, including techniques for reducing power noise and frequency jitter.
Various types of improved VCO circuits have been disclosed in the prior art. For example, in U.S. Pat. No. 5,061,907 issued to R. R. Rasmussen, a multi-stage ring oscillator with ring trip-point compensation is used to control the duty cycle of the VCO output.
In U.S. Pat. No. 5,081,428 issued to A. H. Atriss et al., a VCO circuit is disclosed which uses current mirrors to generate a 50 percent duty cycle output which is derived directly from the VCO frequency. Therefore, there is no need to operate the VCO at 4 times the frequency of the input clock signal, as in the prior art circuit shown in FIG.
1
. This improved VCO can be used in a 2X PLL circuit as shown in FIG.
2
. While the operating frequency of this VCO circuit has been reduced to half the frequency of the prior art circuit shown in
FIG. 1
, the VCO circuit design is complex and challenging.
Another prior art method for doubling the incoming clock frequency is through the use of an exclusive OR (XOR) gate, as shown in FIG.
3
. An incoming clock signal is connected to the first input of the XOR gate, and is also connected to the second input through a delay element. If the input clock has a 50% duty cycle, the output will be a clock at twice the input frequency. However, the duty cycle of this output frequency can vary between 20 percent and 80 percent. For example, if the delay element provides a nominal delay of 40 percent of the output clock period, the process variations in manufacturing the delay element can result in a delay which is as small as one half (20%), or as large as two times (80%), the nominal 40 percent delay. A 20 percent worst case duty cycle clock is unacceptable for most applications, and effectively prohibits further multiplication. Therefore, there is still a need for a simplified and improved circuit and method for frequency multiplication, with an equalized (50%) duty cycle output.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art, and to provide a simplified frequency multiplication circuit with a stable 50% duty cycle output.
SUMMARY OF THE INVENTION
In accordance with an illustrative embodiment of the present invention, a circuit for N times frequency multiplication and 50% duty cycle equalization of an unpredictable input clock signal has a rising or falling edge detector as an input stage. An input clock signal at a frequency fin is edge detected by this detector, which outputs a one shot pulse signal for each transition cycle of the input clock signal. The one shot pulse signals make up a pulse train at a frequency equal to fin, but with a duty cycle much less than 50%.
The one shot pulse train is inputted in parallel to a quantity N−1 first-stage duty cycle control buffers, where N is an integer>=2. The first-stage duty cycle control buffers are arranged in parallel branches, with preset duty cycles equal to 1/N, 2/N,...,N−1/N, respectively. Thus, the one shot pulse train is duty cycle adjusted simultaneously in each parallel branch, with the number of branches depending on the value of N.
The output signal from the first-stage duty cycle control buffer, having a duty cycle equal to 1/N, is inputted to a rising and falling edge detector. This detector outputs a one shot pulse signal for each transition edge of the 1/N duty cycle signal, such that the one shot pulse signals outputted from the rising and falling edge detector occur at a frequency equal to twice that of the input signal frequency (2fin).
If N>2, there will be one or more additional first-stage duty cycle control buffers, with their duty cycle adjusted outputs each connected to a corresponding falling edge detector. Each falling edge detector outputs a one shot pulse signal for each transition cycle of its respective 2/N,...,N−1/N duty cycle adjusted input. The one shot pulse signals are therefore outputted from the falling edge detectors at the same frequency fin as that of the input signal, but are spaced in time according to the duty cycle of their respective input.
An OR gate receives the 2fin output signal from the rising and falling edge detector, and, when N>2, also receives the output signals from the N−2 falling edge detectors. The OR gate outputs a pulse train combining all the inputted edge detected signals, such that the OR gate output signal frequency is equal to N times the input frequency fin.
A second-stage 50% duty cycle control buffer receives the OR gate output signal at frequency N times fin, and adjusts its duty cycle to 50%, at frequency N times fin.
Where an input clock signal has a predictable 50% duty cycle, a circuit for 2N times frequency multiplication is readily achievable by modifying the above described circuit. All that is required is the replacement of the input stage rising or falling edge detector with an input stage rising and falling edge detector. In this case, the input stage rising and falling edge detector receives the 50% duty cycle input clock signal at a frequency fin, and outputs a one shot pulse signal for each transition edge of the input clock signal. The output one shot pulse signals make up a pulse train at a frequency equal to 2 times fin, with a duty cycle less than 50%. The remainder of the circuit functions in exactly the same manner as described above, with the final output frequency at 2N times fin, and at a 50% duty cycle.
An illustrative embodiment of the present invention is more fully described below in conjunction with the following drawings.
REFERENCES:
patent: 3974501 (1976-08-01), Ritzie
patent: 4479216 (1984-10-01), Krambeck et al.
patent: 4831343 (1989-05-01), Baron
patent: 5061907 (1991-10-01), Rasmussen
patent: 5081428 (1992-01-01), Atriss et al.
patent: 5107264 (1992-04-01), Novof
patent: 5926053 (1999-07-01), McDermott et al.
patent: 6060922 (2000-05-01), Chow et al.
patent: 403102909A (1991-04-01), None
Chow Hwang-Cherng
Chu Yuan-Hua
Shuai Chi-Chang
Industrial Technology Research Institute
Lam Tuan T.
Nguyen Hiep
Proskauer Rose LLP
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