Frequency modulation using a phase-locked loop

Details Frequency modulation using a phase-locked loop Frequency modulation using a phase-locked loop

1997-04-30

1999-07-06

Ton, Dang

Multiplex communications

Communication over free space

Combining or distributing information via time channels

375354, 375373, 375376, H04J 306

Patent

active

059205563

ABSTRACT:
A transmitter transmitting signal bursts to a TDMA communication system, and comprising a frequency synthesizing circuit having an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied, a controller controlling the transmission of the transmitter and a stable clock signal generator supplying a stable clock signal. The frequency synthesizing circuit includes a phase-locked loop (PLL) comprising a voltage controlled oscillator (VCO) and a phase detecting unit. The voltage controlled oscillator (VCO) generates an output signal whose frequency is controlled by a control signal, said output signal being modulated in response to the data bit flow received on the input. The phase detecting unit compares the output signal supplied by the voltage controlled oscillator with the stable clock signal supplied by the stable clock signal generator and supplies an error signal in response thereto. A compensating circuit which receives a measure of the bit flow received, compensates the error signal for contributions originating from the bit flow received, and supplies the compensated error signal as a control signal to the voltage controlled oscillator (VCO). The transmitter furthermore includes swithing means controlled by said controller for resetting said error signal before the transmision of a burst.

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