Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
1999-11-18
2002-04-16
Chin, Stephen (Department: 2734)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S146000, C370S320000
Reexamination Certificate
active
06373880
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a modulation circuit using W-CDMA (Wide-band Code Division Multiple Access) as a mobile communication scheme of the next generation and, more particularly, to a frequency spread modulation circuit using multi-code transmission and prepared on the terminal side for IQ multiplex transmission.
2. Description of the Prior Art
CDMA (Code Division Multiple Access) mobile communication uses frequency spreading in which channels are discriminated on the basis of not frequencies or timings but spread codes with low correlation, unlike the conventional FDMA (Frequency Division Multiple Access or TDMA (Time Division Multiple Access). A channel discriminated by a spread code is called a code channel.
In an advanced CDMA scheme such as W-CDMA (Wide-band CDMA), a plurality of spread codes (i.e., a plurality of code channels) are assigned to one terminal to enable high-speed data transmission. This is called a multi-code.
To transmit a multi-code, a plurality of code channels are divided into two groups. After the code channels are spread, they undergo quadrature phase modulation using the sum of the first group as an I signal (in-phase signal) and the sum of the second group as a Q signal (quadrature signal). This scheme is called IQ multiplex or an IQ multiplex scheme.
Normally, before quadrature modulation, the channels are multiplied by scramble codes and randomized (hence, the above I and Q signals are not always directly used as the in-phase and quadrature signals), and the band is limited by a filter.
FIG. 1
shows a schematic view of the IQ multiplex scheme using a multi-code.
N signals DPDCH
1
to DPDCH N input from the left side represent data channels, respectively. A signal DPCCH represents a control channel. In the description of this patent, this channel is not particularly discriminated from the remaining data channels. These signals are binary signals of “0” or “1”.
A frequency spread modulation circuit
301
spreads the input signals using different spread codes in units of channels and then divides them into two groups. The sums of the respective groups are obtained as I and Q signals.
The signals are scrambled and output as signals Iout and Qout. The bands of the signals Iout and Qout are limited by filters
302
and
303
, respectively. After that, the signals are converted into analog signals by D/A converters
304
and
305
. These analog signals undergo quadrature modulating by a quadrature modulator
308
. The resultant high-frequency signal is mixed up and amplified by a transmitter
306
and output from an antenna
307
.
An outline of the transmission system circuit of a terminal apparatus of the IQ multiplex scheme using a multi-code has been described above.
The arrangement of the frequency spread modulation circuit
301
of this prior art will be described with reference to FIG.
2
.
FIG. 2
shows a frequency spread modulation circuit for realizing IQ multiplex using a multi-code.
Input signals represent data channels. The channels DPDCH
1
to DPDCH N and control channel DPCCH, i.e., a total of N+1 signals are input. These signals are divided into two groups. Various methods can be used to divide the channels. For example, odd-numbered data channels are put into the I group, and even-numbered data channels the Q group.
Different predetermined spread codes corresponding to the signals, respectively, are generated by spread code generation circuits
1
to
7
. When both the spread codes and input signals are binary codes of 0 or 1, frequency spreading is realized by calculating exclusive ORs 8 to 14 of the input signals and spread codes.
The frequency spreading results (binary signals of 0 or 1) are input to coefficient circuits
15
to
21
. When the input is a 0, the coefficient circuit outputs a predetermined positive value. When the input is at 1, the coefficient circuit outputs a predetermined negative value. The predetermined values change in units of channels. In the example shown in
FIG. 2
, a value A is set for all data channels, and a value G for the control channels. For a data channel, when the spread result is a 0, +A is output, and when the spread result is a 1, −A is output. For the control channel, when the spread result is a 0, +G is output, and when the spread result is a 1, −G is output. Each of the predetermined values A and G has a plurality of bits. The values are binary numbers and correspond to the transmission levels of the channels.
The values −A and −G are given by the 2's complements of the values A and G.
An adder
22
calculates the sum of the coefficient circuits (
15
to
17
) to which the I group belongs and outputs it as an I signal. An adder
23
calculates the sum of the coefficient circuits (
18
to
21
) to which the Q group belongs and outputs it as a Q signal. The I and Q signals are binary numbers with a large number of bits.
A circuit
24
is a complex multiplier which scrambles the I and Q signals to generate signals Iout and Qout. As the scramble codes, two sets of pseudo noise signals such as codes of M-sequence or Gold codes with low correlation are used. These are signals PNI and PNQ. The signals PNI and PNQ are binary codes of 0 or 1. These signals are converted into signed data signals XI and XQ of +1 or −1 by coefficient circuits
25
and
26
, respectively.
The relationship between the signals PNI and PNQ and the signals XI and XQ is shown in the table of FIG.
3
.
When the signal PNI is a 0, the signal XI is +1.
When the signal PNI is a 1, the signal XI is −1.
When the signal PNQ is a 0, the signal XQ is +1.
When the signal PNQ is a 1, the signal XQ is −1.
The relationships between the inputs and outputs of the complex multiplier
24
are represented by
I
out
+
j
·
Q
out
=
(
I
+
j
·
Q
)
·
(
X
I
+
j
·
X
Q
)
=
(
I
·
X
I
-
Q
·
X
Q
)
+
j
·
(
I
·
X
Q
+
Q
·
X
I
)
∴
I
out
=
I
·
X
I
-
Q
·
X
Q
Q
out
=
I
·
X
+
Q
·
X
I
(
1
)
Multipliers
27
,
28
,
29
, and
30
and adders
31
and
32
in the complex multiplier
24
faithfully execute the above equations.
The signals are scrambled in this way to generate the signals Iout and Qout.
The subsequent processing has been described above with reference to FIG.
1
.
The conventional frequency spread modulation circuit for realizing IQ multiplex using a multi-code has been described above.
In principle, the above-described arrangement poses no problem. However, since the I and Q signals have a relatively large number of bits, the multipliers
27
,
28
,
29
, and
30
and adders
31
and
32
in the arrangement based on the principle become complex, and the processing time increases.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation of the prior art, and has as its object to provide a frequency spread modulation circuit which can reduce the circuit scale and shorten the delay time y simplifying the scramble circuit in a complex multiplier and has the same function as that of the conventional circuit.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a frequency spread modulation circuit for performing frequency spreading using a plurality of spread codes, comprising a first input signal group (I signal group) having one or a plurality of input signals, a second input signal group (Q signal group) having one or a plurality of input signals, a first multiplication circuit group having a plurality of multiplication circuits for spreading the input signals belonging to the first input signal group using different spread codes, respectively, a first coefficient circuit group having a plurality of coefficient circuits for outputting predetermined values in accordance with outputs from the first multiplication circuit group, a
Chin Stephen
Dickstein , Shapiro, Morin & Oshinsky, LLP
Ha Dac V.
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