Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2002-09-18
2004-07-20
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S00100A, C331S017000
Reexamination Certificate
active
06765446
ABSTRACT:
BACKGROUND OF THE INVENTION
Prior art feedback control electronics are known to include the phase locked loop (“PLL”). The typical PLL includes a low pass filter, a phase detector, and a feedback loop coupling a voltage-controlled oscillator (“VCO”) to the phase detector. The PLL locks an input signal to the phase detector with the oscillations of the VCO. Specifically, the phase detector tracks the difference in phase and frequency between the input signal and the signal output by the VCO, and outputs a signal proportional to that difference. The low pass filter removes AC components of the phase detector signal to drive the input to the VCO. The circuit is arranged to drive the VCO towards a zero phase difference, creating a “locked” loop. A PLL thus measures and adjusts phase and frequency.
A common use of the PLL is to generate a fixed multiple of the input signal frequency. In this case, an N counter (or divider) is part of the feedback loop. The counter divides the VCO output by N. One problem with such a PLL occurs when the input signal derives from a variable frequency source—which requires a high or variable N value that may make the PLL unstable.
The PLL comes in various forms. By way of example, the PLL may exist as integrated circuitry within complex processor designs. Often the role of the PLL in such designs is to generate a selected clock rate. The prior art PLL can be overly complex for this purpose. Moreover, the prior art PLL may be unstable since the processor design may seek to utilize a variable frequency source as input to the PLL.
SUMMARY OF THE INVENTION
In one aspect, a frequency lock loop (“FLL”) is provided. The FLL may operate to generate an output frequency (F
out
) that is an integer multiple of an input reference frequency (F
ref
); though the FLL may operate without-regard to phase differences between F
ref
and F
out
. The FLL may include a latch at the input of the F
ref
signal line. A VCO driver or other device (e.g., a digital-to-analog (“D/A”) converter or proportional charge pump) may connect with the latch to drive the input voltage of a VCO. An output of the VCO may couple with a reloadable N counter in a feedback loop coupled with the latch, with the F
ref
signal line connected to load the counter. F
ref
may also clock the latch.
In one aspect, the counter is loaded with an integer value N at a clocking edge (leading or trailing) of the F
ref
signal line. A bus connected with the counter may be used to load the value N. The counter may count a sequence of F
out
cycles before the next end of one F
ref
cycle, at which point the counter may be reloaded with the value N. By way of example, during one cycle of F
ref
, the counter counts down from N to a maximum negative amount without overflowing. A typical counter for example counts from a maximum of “16” or “32”, as “N”, to a maximum negative “16” or “32”, respectively. If for example N is ten and the counter counts from ten to minus four, then the counter may generate an output count of minus four as input to the latch; the value of minus four is loaded to the latch at the next clocking edge of F
ref
. In one aspect, if the counter reaches its maximum negative count, that maximum negative count value is latched as input to the VCO.
A value from the latch may be input to the VCO driver to drive the VCO output of F
out
closer to N*F
ref
. In one example, the VCO driver is a D/A converter, converting the latched value to an analog voltage signal that modifies the voltage control to the VCO. If the output from the counter is minus four, then the D/A converter for example reduces the voltage to the VCO by an amount corresponding to minus four; if the output from the counter is minus nine, then the D/A converter for example reduces the voltage to the VCO by a greater amount corresponding to minus nine; if the output from the counter is six, then the D/A converter for example increases the voltage to the VCO by an amount corresponding to six; and so on.
In one example, the VCO driver is a proportional charge pump. An F
out
clock signal may input to the proportional charge pump such that the charge pump proportionally drives the VCO. By way of example, the proportional charge pump may convert the latched value to a voltage or current input to the VCO that is biased by the number of F
out
cycles within a single F
ref
cycle. Such a technique may be used to accelerate loop lock of the FLL.
Those skilled in the art should appreciate that other VCO drivers exist to accomplish like functions. Regardless of VCO driver form, a frequency “lock” may occur when the counter output is “zero” and the VCO is N times the input frequency. A FLL can be more stable with a larger N value counter.
In one aspect, an improved processor is provided. The processor operates at a first clock frequency and includes at least one FLL to generate one or more second clock frequencies from the first clock frequency and based on the value N. The processor may have an internal clock operating at 1 GHz or more. In one example, the first clock frequency corresponds to bus frequencies of the processor and the second clock frequency corresponds to greater frequencies for use within the processor, up to and including the speed of the internal clock. A processor bus connected with the FLL may load the FLL with a value N.
Certain advantages are realized by the FLL. By way of example, the FLL may be more stable with a greater frequency difference between the input and output frequencies, as the FLL may better detect frequency errors. In contrast, the prior art PLL becomes increasingly unstable as the frequency difference increases, due to a frequency and phase error sensitivity that increases in proportion to the frequency difference. In another example, as technology advances, the clock speed of processor technology tends to increase more quickly than the bus speed connecting that processor to other devices; accordingly, there is an increasing frequency difference between bus speed and processor clock speed. When the bus provides the input signal, the prior art PLL has difficulty tracking the frequency difference to the processor clock speed. The FLL on the other hand is more stable with this increasing frequency difference, thereby assisting the advancement of modern processor design. Clock stability is an important design consideration in processor development. As the clock rate varies, additional margin is desired to account for frequency differences. If there is a 10% variation in the clocking edges of a 3 GHz processor, for example, that processor may be designed to run at a minimum of 3.3 GHz to handle clock variations, adding significant effort and costs to the processor design. As the input to output multiplication factor increases, the prior art PLL becomes more sensitive to noise sources, causing additional jitter in the output. In contrast, increasing the multiplication factor for the FLL increases the number of clock samples used to determine frequency error, thereby decreasing the FLL's sensitivity to random noise events, due to averaging.
REFERENCES:
patent: 3753141 (1973-08-01), Van Elk et al.
patent: 4009449 (1977-02-01), Agans
patent: 4316152 (1982-02-01), Meyer
patent: 4520327 (1985-05-01), Myers
patent: 5535067 (1996-07-01), Rooke
patent: 6268780 (2001-07-01), Olgaard et al.
Hewlett--Packard Development Company, L.P.
Mis David
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