Frequency independent scan chain

Details Frequency independent scan chain Frequency independent scan chain

1996-05-31

1997-12-23

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Shift direction control

377 78, 377 80, G11C 1900

Patent

active

057013357

ABSTRACT:
A shift register is clocked by propagating two clock networks in opposite directions: one from input towards the output, the other from the output towards the input. The parasitic delays at the end of these networks are picked to be approximately equal. An extra latch is added to the shift register where the two clock networks meet to prevent a race condition. Both clock networks consist of non-overlapping clocks. Non-overlapping clock generator circuits are used to restore the non-overlap of the clocks when parasitic effects start to cause clock overlap as the clocks are propagated over long distances. An extra latch in the shift register at the non-overlapping clock generators prevents the delay of the non-overlapping clock generator from causing a race condition.

REFERENCES:
patent: 5231314 (1993-07-01), Andrews
patent: 5313470 (1994-05-01), Simpson
patent: 5367551 (1994-11-01), Okumura et al.
patent: 5530706 (1996-06-01), Josephson et al.
IEEE Std 1149.1-1990, IEEE Sandard Test Access Port And Boundary-Scan Architecture, available from The Institute of Electrical and Electronic Engineers, Inc., 345 East 47th Street, New York, NY 10017-2394.

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