Frequency-independent monitor circuit

Details Frequency-independent monitor circuit Frequency-independent monitor circuit

1990-08-13

1992-03-24

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

331 64, H03K 1900

Patent

active

050991531

ABSTRACT:
A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge. Thus, when the circuit being monitored becomes inactive, the counter chain will start to count down, and will eventually reach zero and generate a watchdog interrupt or reset.

REFERENCES:
patent: 4816776 (1989-03-01), Kessler

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