Frequency driven layout and method for field programmable gate a

Boots – shoes – and leggings

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364488, 364489, 364490, G06F 1750

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056594844

ABSTRACT:
A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4947365 (1990-08-01), Masubuchi
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5053980 (1991-10-01), Kanazawa
patent: 5095454 (1992-03-01), Huang
patent: 5144563 (1992-09-01), Date et al.
patent: 5168563 (1992-12-01), Shenoy et al.
patent: 5187784 (1993-02-01), Rowson
patent: 5197015 (1993-03-01), Hartoog et al.
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5239481 (1993-08-01), Brooks et al.
patent: 5239493 (1993-08-01), Sherman
patent: 5251147 (1993-10-01), Finnerty
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5498979 (1996-03-01), Parlour et al.
patent: 5521837 (1996-05-01), Frankle et al.
Agrawal, V.D., "Synchronous Path Analysis in MOS Circuit Design," 19th Design Automation Conference, 1982, pp. 629-635.
Brown et al., "A Detailed Router for FPGAs", IEEE Trans. on Computer-Aided Design, vol. 11, No. 5, May 1992, pp. 620-628.
Donath et al., "Timing Driven Placement Using Complete Path Delays", 27th ACM/IEEE Design Automation Conference, 1990, pp. 84-89.
Frankle, "Iterative and Adaptive Slack Allocation for Performance-driven Layout and FPGA Routing," 29th ACM/IEEE Design Automation Conference, pp. 536-542.
Schlag et al., "Empirical Evaluation of Multilevel Logic Minimization Tools for a Look-Up-Table-Based FPGA Technology," IEEE Trans on CAD of ICs and Systems, vol. 12, No. 5, May 1993, pp. 713-721.
Singh et al., "Optimization of FPGA Logic Block Architecture for Speed," IEEE 1991 Custom ICs Conference, pp. 6.1.1-6.1.6.
Agrawal, "Synchronous Path Analysis in MOS Circuit Simulator", 19th DAC, 1982 IEEE, pp. 629-635.
Burstein et al., "Timing Influenced Layout Design" 22nd DAC, 1985 IEEE, pp. 124-130.
Chan et al., "Architectural Tradeoffs in Field-Programmable-Device-Based Computing Systems," 1993 IEEE, pp. 152-161.
Luk, "A Fast Physical Constraint Generator for Timing Driven Layout," 28th ACM/IEEE DAC, 1991 ACM, pp. 626-631.
Teig et al., "Timing-Driven Layout of Cell-Based ICs" VLSI Systems Design, May 1986, pp. 63-73.
Hitchock, R., "Timing Verification and the Timing Analysis Program," Proceedings 19th Design Automation Conference, 1982, pp. 594-604.
Roth, J.P., "Diagnosis of Automata Failures: A Calculus and a Method," IBM Journal of Research and Development, Jul. 1966, pp. 278-291.
Du, D., Yen, S. and Ghanta, S., "On the General False Path Problem in Timing Analysis," Proceedings 26th Design Automation Conference, 1989, pp. 555-560.
Liu, L., Chen, H. and Du, D., "The Calculation of Signal Stable Ranges in Combinational Circuits," Proceedings ICCAD-91, 1991, pp. 312-315.
McGreer, P. and Brayton, R., "Efficient Alogrithms for Computing the LongestViable Path in a Combinational Network," Proceedings 26th Design Automation Conference, 1989, pp. 561-567.
Stewart, R. and Benkoski, J., "Static Timing Analysis Using Interval Constraints," Proceedings ICCAD-91, 1991, pp. 308-311.
Xilinx, Inc., "Programmable Gate Array Data Book," Xilinx, Inc., 1992, pp. 6-13.
Rubenstein, J., Penfield, P. and Horowitz, M., "Signal Delay in RC Tree Networks," IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.
Bening, L.C., Alexander, C.R., and Lane, T.A., "Developments in Logic Network Path Delay Analysis," Proceedings 19th Design Automation Conference, 1982, pp. 605-615.
Jackson, M.A.B. and Kuh, E.S., "Performance-Driven Placement of Cell Based IC's," Proceedings 26th Design Automation Conference, 1989, pp. 370-375.
Youssef, H. and Shragowitz, E., "Timing Constraints for Correct Performance," Proceedings ICCAD-90, 1990, pp. 24-27.
Frankle, J., "Integrating Path Analysis with Physical Design," SIGDA Newslwtter, vol. 21, No. 3, p. 35.
Malgorzata Marek-Sadowska and Shen P. Lin, "Timing Placement," Proc. of ICCAD '89, pp. 94-97,1989.
J. Garbers, B. Korte, H. J. Promel, E. Schwietzke, A. Steger, "VLSI-Placement Based on Routing and Timing Information," Proc. of the European Design Automation Conference, pp. 317-321, 1990.
Michael A. B. Jackson, Arvind Srinivasan, E. S. Kuh, "A Fast Algorithm for Performance-Driven Placement," proc. of ICCAD '90, pp. 328-331, 1990.
Arvind Srinivasan, "An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs," Proc. of the 28th Design Automation Conference, pp. 636-639, 1991.
Ren-Song Tasy, Juergen Koehl, "An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement," Proc. of the 28th Design Automation Conference, pp. 620-625, 1991.
Robert B. Hitchcock, Sr., Gordon L. Smith, David D. Cheng, "Timing Analysis of Computer Hardware," IBM J. Res. Develop., vol. 26, No. 1, pp. 100-105, 1982.
Vishwani D. Agrawal., "Synchronous Path Analysis in MOS Circuit Simulator," 19th Design Automation Conference, Paper 35.4, pp. 629 through 635, 1982.
Michael A.B. Jackson and Ernest S. Kuh, "Performance-Driven Placement of Cell Based IC's," 26th ACM/IEEE Design Automation Conference, Paper 24.2, pp. 370 through 375, 1989.
Jorge, Rubinstein, Paul Penfield, Jr., and Mark A. Horowitz, "Signal Delay in RC Tree Networks," IEEE Transactions on Computer Aided Design, vol. CAD-2, No. 3, pp. 202 through 211, Jul. 1983.
Steven Teig, Randall L. Smith, and John Seaton, "Timing-Driven Layout of Cell Based ICs," VLSI Systems Design, pp. 63 through 73, May 1986.
Habib Youssef, Eugene Shragowitz, "Timing Constraints for Correct Performance," pp. 24-27, 1990 IEEE.
H. Youssef, "Timing Analysis fo cell Based VLSI Designs," Computer and Information Sciences, University of Minnesota, Ph.D. Thesis, Jan. 1990.
Suphachai Sutanthavibul, E. Shragowitz, "Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement," 28th ACM/IEEE Design Automation Conference, Paper 37.4, pp. 632-635, 1991.
B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," The Bell System Technical Journal, pp. 291-307, Feb. 1970.
Neil R. Quinn, Jr., and Melvin A. Breuer, "A Force Directed Component Placement Procedure for Printed Circuit Boards," IEEE Transactions on Circuits and Systems, vol. CAS-26, No. 6, pp. 377-388, Jun. 1979.
Peter S. Hauge, Ravi Nair, Ellen J. Yoffa, "Circuit Placement for Predictable Performance," Proc. of ICCAD '87, pp. 88-91, 1987.
A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak, M. Wiesel, "Chip Layout Optimization Using Critical Path Weighting," 21st Design Automation Conference, Paper 9.2, pp. 133-136, 1984.
Stephen D. Brown, Jonathan Rose, and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEE Trans. on CAD of ICs and Systems, vol. 12, No. 12, pp. 1827-1838, Dec. 1993.
Norman P. Jouppi, "Timing Analysis for nMOS VLSI," 20th Design Automation Conference, Paper 27.3, pp. 411-418, 1983.

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