Frequency doubling two-phase clock generation circuit

Details Frequency doubling two-phase clock generation circuit Frequency doubling two-phase clock generation circuit

2002-06-20

2003-12-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S119000

Reexamination Certificate

active

06661262

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to chip clock distribution, generation and repowering circuits.
TRADEMARKS
IBM is a registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
Microprocessor frequencies are scaling with CMOS device speed and are outpacing the capabilities of global chip clock distribution. The problem is two fold. First, the number of circuits per chip is growing roughly as the square of the lithography improvement and thus the clock needs to be distributed to more circuits. Second, the wire performance is relatively constant. The thickest wiring layers which are generally used to route the global clocks behave as a low pass filter with a cutoff frequency which does not improve with device speed. Previously this cutoff frequency limit has been extended through the use of very wide wires. It would be advantageous to extend the global clock distribution frequency limit without reducing the number of wiring tracks available to I/O and signals. It would also be advantageous to reduce the power associated with generating and globally distributing the clock.
SUMMARY OF THE INVENTION
The invention provides a frequency doubling two-phase clock generation circuit which avoids the above described frequency limitation. In accordance with the preferred embodiment of the invention our clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The preferred circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.


REFERENCES:
patent: 5359232 (1994-10-01), Eitrheim et al.
patent: 5365181 (1994-11-01), Mair
patent: 6411139 (2002-06-01), Unterricker

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