Frequency-doubling delay locked loop

Details Frequency-doubling delay locked loop Frequency-doubling delay locked loop

2006-07-28

2008-11-25

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S116000, C327S119000

Reexamination Certificate

active

07456666

ABSTRACT:
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

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