Frequency-doubling delay locked loop

Details Frequency-doubling delay locked loop Frequency-doubling delay locked loop

2000-05-01

2002-08-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06441659

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of clock generation circuit for generating a high speed clock of a reference clock signal, and more particularly, to such circuits incorporating a delay locked loop (DLL).
BACKGROUND TO THE INVENTION
In many relatively self-contained electronic subsystems such as integrated circuits and multi-chip modules, an internal clock is used to synchronize operations. Often the frequency of the internal clock is higher than the frequency of an external interface clock which is used to synchronize the transfer data and control information to and from the subsystem. It is often necessary to establish a defined phase and frequency relationship between the internal clock and the slower external interface clock for efficient low latency operation of the interface. As an example, a common requirement is to have the internal clock signal be exactly twice the frequency of the interface clock. Even tighter restrictions might require that rising edges of the inter clock line up with every second rising edge of the internal clock.
When the interface clock is generated outside the subsystem, it is necessary to synthesize the higher-frequency internal clock signal within the subsystem, while simultaneously meeting the desired phase and frequency relationship. It may also be necessary for the internal clock to track variations in phase and/or frequency of the interface clock.
The synthesis of an appropriate internal clock based on a slower interface clock is often accomplished by using a phase-locked loop or PLL circuit within the subsystem. Many PLL implementations have been presented in the field. Generally, in a PLL scheme, the external interface clock provides the reference clock input to the PLL which generates the internal clock signal. An appropriately divided down version of the internal clock signal (or a delayed version thereof serves as the local feedback to the PLL. A representative example of such a scheme is disclosed in U.S. Pat. No. 5,412,349 to Young et al and the accompanying paper “A PLL Clock Generator with 5 to 110 MHz Range for Microprocessors,”
IEEE SC Vol
. 27, No. 11, Nov. 1992, pg. 1599-1606. The PLL based clock generator described therein includes a phase frequency detector, charge pump, loop filter, and a voltage controlled oscillator (VCO), from which an internal clock having a 50% duty cycle is generated. The VCO operates at twice the external clock frequency and a divide-by-2 circuit is used to accurately generate the 50% duty cycle internal clock which is used internally within the microprocessor. Another example of a PLL clock generation schemne is presented in U.S. Pat. No. 5,634,117 to Conary et al. In this reference, a microprocessor is described which operates at the speed of the system bus or at a speed which is a multiple of the bus speed on a selectable basis. Specifically, the microprocessor core operates at the same or twice the frequency of the address/data buses by employing a PLL which generates clock signals for controlling operations within the microprocessor.
In both of the above mentioned references, the external interface clock is a continuous free-running clock, usually generated with a crystal oscillator somewhere on the subsystem and routed to the microprocessor, memory and other elements. Then, a PLL-based clock generation system is used to generate the internal clocks. However, PLL-based clock generation systems are generally unsuitable if the interface clock is intermittent (i.e. not continuous) and if it is necessary to restore the desired phase and frequency relationship between the interface clock and internal clock quickly when the interface clock reappears. In addition, PLLs are also unsuitable if it is necessary for the internal clock to accurately track high frequency phase jitter in the interface reference clock.
More generally, analog PLLs suffer from a number of general drawbacks in today's mainly digital memory design environment. Firstly, PLLs employ analog elements which typically consume substantially more power than digital elements due to their de bias current requirements. Secondly, recent trends towards decreasing power supply voltages for reducing power consumption in high density memory applications runs against the need for relatively high power supply voltage for the analog elements of PLLs. Thirdly, the length of time required to achieve a locked condition for PLLs is relatively large due to the need for a large closed loop time constant to minimize jitter. In general, in digital system such as memories microprocessor and ASICs, these types of PLLs introduce unnecessary analog design complications in a mainly digital design and therefore have recently been avoided.
An alternate approach to clock data synchronization can be achieved through the use of a Delay Locked Loop (DLL). Conventional DLL circuits have been in the industry as a digital alterative to analog PLLs. These circuits are typically consist of a tapped digital delay line made up of digital delay elements. The taped outputs are input into some multiplexing circuitry which is used to select the appropriate phase delay of the input clock to provide to the internal circuitry. The internal clock is also fedback to a phase detector, similar in function to phase detectors in PLLs. An example of this structure is disclosed in MOSAID Technologies Inc. U.S. Pat. No. 5,796,673 to Foss et al. An alternate DLL configuration is described in another MOSAID Technologies Inc. U.S. Pat. No. 5,777,501 to Abousiedo. This structure uses a folded delay line implementation in which the delay line is folded at approximately half its total delay length, and shunting connections are provided between the portion of the delay line going one way and the portion returning the other way. The shunting connections are controlled by a shift register which selects the correct tap position for providing the desired clock for internal distribution.
Most recently, high speed memory inter circuits have furthered the improvements of DLL-based internal clock generating schemes. Specifically, a high bandwidth memory inter application employing a differential charge pump and a phase shifter is presented in U.S. Pat. No. 5,614,855 to Lee. et al. This approach, although fairly robust, is however an analog solution, employing a number of complex analog elements such as the differential charge pump, the duty cycle correction amplifiers, and the phase mixer, and as a result, suffers from the same general drawbacks of implementing analog circuits in the digital domain as were mentioned above. An improved digital implementation of a DLL for use in high bandwidth memory interface circuitry is presented by Gillingham et al. in “A 800 Mbyte/sec 72 Mbit SLDRAM with Digitally Calibrated DLL,” ISSCC February. 1999.
In this circuit, the delay locked loop locks to a 5 ns of the reference clock and provides 32 equally spaced outputs. Using a simple DLL with fixed delay elements result in jitter during operation as temperature or voltage variations cause the DLL to jump from one delay element to another. This problem is overcome by controlling the delay of each unit delay stage so that 32 stages always produce a 5 ns delay. A seven bit current output DAC shown in
FIG. 1
, provides the reference current for the delay stages, The DAC has a non-linear transfer function to provide cost and delay resolution over process, temperature, and voltage variation. The operational circuit may be explained as follows: during initialization, a single tap from the 32 stage delay line which matches the reference clock is selected. This may be termed the virtual zero degrees tap. Normally, a few stages may be used as a lead in delay to compensate for delay in input buffers and clock distribution. On initialization, the current control for his lead in delay is set to mid range so that during operation as temperature or voltage fluctuations occur, the lead in delay is adjusted to maintain the virtual zero degrees tap in phase with the reference clock. Thus, the 32 stage del

Affiliated with

Also associated with

Rating

Frequency-doubling delay locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Frequency-doubling delay locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency-doubling delay locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2937466