Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
1999-06-28
2001-04-03
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S238000
Reexamination Certificate
active
06211708
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronics and more particularly to frequency doubling circuits and methods.
BACKGROUND OF THE INVENTION
Frequency doubling circuits are commonly used to generate a frequency doubled output signal having a frequency twice that of an input (or reference) signal. Various frequency doubling circuits are discussed, for example, in the following U.S. Patents: U.S. Pat. No. 5,475,349 to Cohn entitled “Frequency Multipliers Using Diode Arrays”; U.S. Pat. No. 5,194,820 to Besson et al. entitled “Frequency Doubling Device”; U.S. Pat. No. 4,691,170 to Riley entitled “Frequency Multiplier Circuit”; U.S. Pat. No. 5,365,181 to Mair entitled “Frequency Doubler Having Adaptive Biasing”; U.S. Pat. No. 4,048,571 to Jacobson entitled “Frequency Doubler”; U.S. Pat. No. 4,734,591 to lchitsubo entitled “Frequency Doubler”; and U.S. Pat. No. 5,552,734 to Kimura entitled “Local Oscillator Frequency Multiplier And Mixing Circuitry Comprising a Squaring Circuit”. Each of these patents is hereby incorporated herein in its entirety by reference.
It is known, for example, to double the frequency of a reference signal A using a delay circuit
21
and an Exclusive-OR gate
23
as shown in
FIGS. 1 and 2
. In particular, the digital reference signal A is delayed by a period of time &tgr; to generate the delayed signal B. The reference signal A can have rising edges occurring at times Tr and falling edges at times Tf. The resulting delayed signal B can thus have rising edges at times Tr+&tgr; and the falling edges at times Tf+&tgr;. Accordingly, the output of the Exclusive-OR gate
23
can have a logical 1 output during the time intervals from Tr to Tr+&tgr;, and from Tf to Tf+&tgr;, and the output of the Exclusive-OR gate
23
can have a logical 0 output during the remainder of the time when the reference signal A and the delayed signal B are both either high or low. In other words, the output signal C generated by the Exclusive-OR gate
23
will have two pulses of duration &tgr; for each period of the reference signal A in effect providing an output frequency twice that of the reference signal.
In the circuit of
FIG. 1
, however, it may be difficult to provide an output signal C having a 50% duty cycle. In particular, the duty cycle of the output signal C is dependent on the duration of the delay &tgr; provided by the delay circuit
21
, and the duration of the delay &tgr; may be difficult to precisely control. If a delay &tgr; can be one quarter of the period (T/4) of the reference signal A, the output signal will have a 50% duty cycle. Desired accuracies may be difficult to provide, however, because of the difficulty of providing low tolerance components such as capacitors and resistors to build a delay circuit.
For example, resistors and capacitors may both be subject to semiconductor manufacturing process fluctuations resulting in 3&sgr; tolerances as great as ±20%. Because the delay that is implemented depends on the RC product, the combined tolerance for the delay may be on the order of ±40%. In other words, a designed delay of 0.25 T may have process tolerance extremes of 0.16 T and 0.36 T resulting in duty cycle extremes of 32% and 72% which are significantly different from 50% (where T is the period of the reference signal).
When providing a frequency doubled output signal for a Radio Frequency (RF) mixer in the signal path of a radio communications transceiver, an accurate 50% duty cycle may be important to suppress even order intermodulation products. Accordingly, a bandpass filter may be needed at the output of the Exclusive-OR gate
23
to suppress even order harmonics of the frequency doubled output signal C thus adding circuitry. Furthermore, suitable bandpass filters may be difficult to implement on an integrated circuit device thereby increasing the size of the system including the frequency doubling circuit and filters.
In addition, the frequency doubled output signal is often used in a differential form in Radio Frequency (RF) integrated circuit applications. Such a differential form can be provided using the circuit illustrated in
FIG. 3
including delay circuits
31
and
33
and Exclusive-OR gates
35
and
37
. The circuit of
FIG. 3
is essentially the combination of two
FIG. 1
circuits being driven by a reference signal D and its inverse D-bar. This circuit, however, is subject to the same difficulties in providing a 50% duty cycle discussed above with regard to FIG.
1
. In addition, the two delay circuits
31
and
33
should be closely matched to provide outputs that are truly differential. The desired matching, however, may be difficult to achieve.
Accordingly, there continues to exist a need in the art for improved frequency doubling circuits, methods, and systems.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved frequency doubling circuits, methods, and systems.
It is another object of the present invention to provide frequency doubling circuits, methods, and systems that can have improved output signal duty cycle performance.
It is still another object of the present invention to provide frequency doubling circuits, methods, and systems that can reduce generation of noise.
These and other objects can be provided according to the present invention by a frequency doubling circuit including a quadrature phase generator and a mixer coupled to the quadrature phase generator. The quadrature phase generator receives a reference signal having a reference frequency and generates first and second quadrature phase shifted signals having the reference frequency. The mixer receives the first and second quadrature phase shifted signals and generates an output signal having an output frequency twice that of the reference frequency.
The frequency doubling circuit of the present invention can thus provide an output signal with an accurate 50% duty cycle because a relative 90 degree phase shift can be provided between the two quadrature phase shifted signals. Moreover, the relative 90 degree phase shift can be provided accurately without requiring precision with respect to absolute values of components used in the quadrature phase generator. Instead, the accurate 90 degree phase shift can be provided by precisely matching the component values used in the quadrature phase generator, and precise matching of component values can be readily provided using components on a common integrated circuit substrate.
The frequency doubling circuit of the present invention can also be implemented as a differential frequency doubling circuit providing both a frequency doubled output signal and an inverse of the frequency doubled output signal. In particular, the quadrature phase generator can receive the reference signal having the reference frequency and an inverse reference signal that is 180 degrees out of phase with respect to the reference signal. In response, the quadrature phase generator generates third and fourth quadrature phase shifted signals so that the second, third, and fourth quadrature phase shifted signals are respectively shifted 90 degrees, 180 degrees, and 270 degrees with respect to the first quadrature phase shifted signal. The mixer can receive the four quadrature phase shifted signals to generate the output signal having the output frequency twice that of the reference frequency and to generate an inverse output signal that is 180 degrees out of phase with respect to the output signal. By generating the differential frequency doubled output signals, the effects of common mode noise can be reduced.
Frequency doubling circuits of the present invention can be used to double the frequency of either analog or digital signals. For example, the mixer can be an Exclusive-OR gate in a digital context or a multiplier in an analog context. More particularly, the mixer can be a Gilbert cell multiplier.
The quadrature phase generator can include a plurality of resistors and capacitors on an integrated circuit substrate wherein the resistors ha
Ericsson Inc.
Myers Bigel & Sibley & Sajovec
Nguyen Linh
Tran Toan
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