Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Patent
1995-05-05
1997-06-03
Tran, Toan
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
327122, H03B 1900
Patent
active
056358660
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a frequency doubler which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.
SUMMARY OF THE INVENTION
According to the present invention there is provided a frequency doubler circuit for receiving first to fourth input signals in quadrature and comprising: a first set of logic gates having inputs for receiving the input signals and providing outputs therefrom; and a second set of logic gates which have as their inputs only the outputs from the first set of logic gates and which supply as their outputs two signals in antiphase at twice the frequency of the input signals.
In the described embodiment the first set of logic gates comprises a first logic gate connected to receive the first and second input signals, a second logic gate connected to receive the second and third input signals, a third logic gate connected to receive the third and fourth input signals and a fourth logic gate connected to receive the first and fourth input signals, the signals supplied to each logic gate being 90.degree. apart in phase and having a duty cycle close to 50%. The second set of logic gates comprises a fifth logic gate connected to receive the outputs of the first and third logic gates and a sixth logic gate connected to receive the outputs of the second and fourth logic gate.
The logic gates are preferably NAND gates, but it is also possible to use NOR gates. However, the switching frequency of the logic gate will limit the maximum operating frequency of the circuit. NAND gates are preferred because they have faster switching speed than NOR gates.
The frequency doubler confers a particular advantage when used to double the frequency of quadrature outputs of a quadrature oscillator, which outputs are subject to buffering and conversion. It is usually difficult to make the oscillator, buffer and convertor operate fast enough but with the present frequency doubler they need operate only at a relatively low frequency. The frequency doubler is then the only circuit which is required to run at a high frequency. This is easier to achieve because it can be designed in high speed CMOS logic and could probably have the facility to be powered by a full supply voltage, whereas the oscillator may be restricted to operate at low supply voltages (of less than 3 V ). An oscillator with which the present invention has particular advantage is described in our copending Application entitled "Quadrature Oscillator," by Trevor Kenneth Monk and Andrew Mendlicott Hall having a PCT Application No. of PCT/GB 94/00892 and a filing date of Apr. 27, 1994, the contents of which are herein incorporated by reference.
For a better understanding of the present invention, and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a first embodiment of a frequency doubler;
FIG. 2 shows the waveforms of signals in the frequency doubler of FIG. 1;
FIG 3 is a circuit diagram of a second embodiment of a frequency doubler; and
FIG. 4 shows the waveforms of signals in the frequency doubler of FIG. 3.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a frequency doubler connected to receive 4-phase quadrature signals .o slashed.1, .o slashed.2, .o slashed.3, .o slashed.4. The input signals .o slashed.1 to .o slashed.4 can come for example from CMOS-level convertors which are connected to the outputs of a quadrature oscillator. The input signals .o slashed.1 to .o slashed.4 are fed to a first layer of NAND gates 2,4,6,8. The first NAND gate 2 receives as its inputs .o slashed.1, .o slashed.2 which are 90.degree. apart. The second NAND gate 4 receives as its inputs the input signals .o slashed.2, .o slashed.3 which are 90.degree. apart. The third NAND gate 6 receives the input signals .o slashed.3, .o slashed.4 which are 90.degree. apart. The fourth NAND gate 8 rece
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Hall Andrew M.
Monk Trevor K.
Carlson David V.
Santarelli Bryan A.
SGS-Thomson Microelectronics Limited
Tran Toan
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