Frequency division circuit

Details Frequency division circuit Frequency division circuit

1976-07-23

1978-10-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

58 23A, 307224C, 307279, H03K 2302, H03K 1760

Patent

active

041198670

ABSTRACT:
An odd number of inverting memory blocks are connected in series in a closed ring circuit. Each inverting elememt comprises a P channel field effect transistor and an N channel field effect transistor which are connected in parallel opposition. Control signals of the same phase are applied to the gate electrodes of the P and N channel field effect transistors. An inverter circuit comprising a pair of field effect transistors having gate electrodes is connected to one of two parallel connected, conductive electrodes of a temporary memory switching circuit. Control gate electrodes of the inverting memory block are controlled by control signals having the same phase and at a frequency to be divided for producing a frequency divided output from the output of one of the inverting memory blocks.

REFERENCES:
patent: 3742248 (1973-06-01), Eaton, Jr.
patent: 3749937 (1973-07-01), Rogers et al.
patent: 3757510 (1973-09-01), Dill
patent: 3833822 (1974-09-01), Carbrey
Suzuki et al., "Clocked CMOS Calculator Circuitry", IEEE Journal of Solid-State Circuits, vol. SC-8, No. 6, 12/1973, pp. 462-469.

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