Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
1999-09-16
2001-11-06
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000, C327S118000
Reexamination Certificate
active
06313673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for frequency-dividing a supplied signal, and more particularly, it relates to a frequency-dividing circuit capable of readily generating a frequency-divided signal having a desired frequency-dividing ratio with a small occupying area.
2. Description of the Prior Art
FIG. 36
schematically illustrates the structure of a conventional 1/3 frequency-dividing circuit. Referring to
FIG. 36
, the conventional 1/3 frequency-dividing circuit includes two stages of cascaded JK flipflops FF
1
and FF
2
. JK flip-flop FF
1
receives a clock signal CLK at a clock input CP, a signal from an output/Q
2
of JK flip-flop FF
2
at an input J, and a fixed value “1” at an input K. JK flip-flop FF
2
receives the clock signal CLK at a clock input CP, a signal from an output Q
2
of JK flip-flop FF
1
at an input J and a fixed value “1” at an input K. JK flipflops FF
1
and FF
2
receive a reset signal RST at reset inputs R. Operations of the 1/3 frequency-dividing circuit shown in
FIG. 36
are now described with reference to a timing chart shown in FIG.
37
.
First, the reset signal RST is activated to initialize output signals Q
1
and Q
2
of JK flipflops FF
1
and FF
2
to a low level. JK flipflops FF
1
and FF
2
are such down edge flipflops that the states of the outputs Q
1
and Q
2
thereof are decided on the falling edge of the clock signal CLK. When the clock signal CLK falls in a cycle #1, the output signal Q
1
of JK flip-flop FF
1
is inverted in state and rises to a high level since the signal/Q
2
supplied to the input J is high. The output signal Q
2
of JK flip-flop FF
2
remains low since the signal Q
1
supplied to the input J on the falling edge of the clock signal CLK is low.
When the clock signal CLK falls in a cycle #2, the output signal Q
1
of JK flip-flop FF
1
is inverted in state and goes low since the signal/Q
2
supplied to the input J is high. On the other hand, the output signal Q
2
of JK flip-flop FF
2
is inverted in state and goes high since the signal Q
1
is high on the falling edge of the clock signal CLK, and the signal/Q
2
responsively goes low.
When the clock signal CLK falls to a low level in a clock cycle #3, the output signal Q
1
of JK flip-flop FF
1
remains low since the signal/Q
2
supplied to the input J is low. On the other hand, the output signal Q
2
of JK flip-flop FF
2
falls to a low level since the signal Q
1
is low. The signal /Q
2
responsively goes high.
When the clock signal CLK falls in a clock cycle #4, the output signal Q
1
of the JK flip-flop FF
1
is inverted in state and rises to the high level from the low level since the signal/Q
2
supplied to the input J is high. On the other hand, the output signal Q
2
of JK flip-flop FF
2
remains low since the signal Q
1
is low on the falling edge of the clock signal CLK. Thereafter these operations are repeated in clock cycles #5 to #9.
In the 1/3 frequency-dividing circuit shown in
FIG. 36
, the signals Q
1
and Q
2
remain high for one cycle period of the clock signal CLK in three cycles of the clock signal CLK. Thus, these signals Q
1
and Q
2
each have a cycle period three times as large as that of the clock signal CLK and correspond to signals obtained by frequency-dividing the clock signal CLK by 3.
A frequency-dividing circuit is widely employed for frequency-dividing a basic clock signal and driving a circuit in various cycles. Such a frequency-dividing circuit is employed in a serial-parallel conversion circuit converting serial data to parallel data, for example. The frequency-dividing circuit may supply a basic clock signal and a frequency-divided signal to internal circuits operating at low and high speeds respectively for driving the circuits synchronization with the clock signal.
Such frequency-divided clock signal preferably has a duty ratio of 50% providing equal high-level and low-level periods, in order to drive an internal circuit at a high speed. In the 1/3 frequency-dividing circuit shown in
FIG. 36
, however, the duty ratio of the frequency-divided signals Q
1
and Q
2
is about 33%. Further, each of JK flipflops FF
1
and FF
2
generally has the structure of a master flip-flop and a slave flip-flop, and includes cross-connected logic circuits. Thus, JK flip-flop disadvantageously has a large number of components (transistors) and a large occupying area. In order to attain the duty ratio of 50%, a counter may be employed as shown in FIG.
38
A.
FIG. 38A
illustrates an exemplary structure of a frequency-dividing circuit utilizing a counter. Referring to
FIG. 38A
, the frequency-dividing circuit includes an N-ary counter
900
counting a clock signal CLK and a T flip-flop
902
inverting the logic state of its output signal DVC in accordance with a count-up instruction signal &phgr;UP from the N-ary counter
900
. When counting N clock signals CLK, the N-ary counter
900
drives the count-up instruction signal &phgr;UP to an active state. As shown in
FIG. 38B
, the logic state of the signal DVC from T flip-flop
902
is inverted each time N clock signals CLK are supplied. Thus, the signal DVC from T flip-flop
902
corresponds to a signal obtained by frequency-dividing the clock signal CLK with a frequency-division ratio of 1/2N. Further, each of high- and low-level periods corresponds to N cycles of the clock signal CLK, and the duty ratio of the output signal DVC can be substantially set to 50%.
Wit the N-ary counter shown in
FIG. 38A
, however, it is difficult to correctly set the duty ratio to 50% due to deviation of the timing for generating the count-up instruction signal &phgr;UP or the like. Further, the N-ary counter formed by a D flip-flop and the like has a large number of components and the occupying area thereof cannot be reduced. When utilizing such an N-ary counter, further, the frequency-division ratio is 1/2N and a frequency-dividing circuit dividing a signal with a frequency-division ratio of 1/(2N+1) cannot be implemented.
When extending the frequency-dividing circuit employing a synchronous counter shown in
FIG. 36
to reduce the frequency division ratio thereof (lengthening the cycle period of the frequency-divided signal), a logic gate must be inserted between JK flipflops depending on the frequency-division ratio. Thus, it is difficult to extend the frequency-dividing circuit to implement a frequency-dividing circuit having a desired frequency-division ratio.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a frequency-dividing circuit having excellent versatility with a small occupying area.
Another object of the present invention is to provide a frequency-dividing circuit capable of correctly and readily generating a frequency-divided signal having a duty ratio of 50%.
Still another object of the present invention is to provide a frequency-dividing circuit readily generating a frequency-divided signal having a desired frequency division ratio.
A further object of the present invention is to provide a frequency-dividing circuit readily extendable to a different frequency division ratio.
A frequency-dividing circuit according to a first aspect of the present invention includes a first delay stage operating in synchronization with a clock signal having a cycle T for delaying a supplied signal by K cycles K·T of the clock signal and outputting the delayed signal, a second delay stage operating in synchronization with the clock signal for delaying a supplied signal by M cycles M·T of the clock signal and outputting the delayed signal, a feedback circuit for feeding back the output signal of the second delay stage to an input of the first delay stage and a logic circuit receiving the output signal of the first delay stage and a feedback signal of the feedback circuit for performing prescribed logical processing on the received signals and supplying the logically processed signals to the second delay stage. K represents an integer, and M represents a natural number. In the logic circuit, t
Lam Tuan T.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Hiep
LandOfFree
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