Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2006-09-19
2006-09-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000
Reexamination Certificate
active
07109762
ABSTRACT:
A frequency-dividing circuit arrangement is disclosed that includes a divider chain having a plurality of frequency divider stages. The frequency dividers can be changed over between the division ratios 2 and 3. At least that frequency divider that is arranged on the output side of the divider chain has an additional through-switching input that makes it possible to switch through the input signal to the output of the divider stage without influencing the delay-time effects of the divider stage. The advantages of a cascaded 2/3 divider chain, such as a high cut-off frequency, a simple design and the ability to arbitrarily expand, are thus achieved without accepting a lower limit of the range of possible division values.
REFERENCES:
patent: 3909791 (1975-09-01), Van den Berg
patent: 4016495 (1977-04-01), Machanian
patent: 4575867 (1986-03-01), Hogue
patent: 4580282 (1986-04-01), Lawton et al.
patent: 5524035 (1996-06-01), Casal et al.
patent: 5754615 (1998-05-01), Colavin
patent: 5909144 (1999-06-01), Puckette et al.
patent: 5948046 (1999-09-01), Hagberg
patent: 6570946 (2003-05-01), Homol et al.
patent: 6614274 (2003-09-01), Shi et al.
patent: 6760397 (2004-07-01), Wu et al.
patent: 6842054 (2005-01-01), Wang
patent: 2005/0058236 (2005-03-01), Ke
patent: 41 29 657 (1992-03-01), None
patent: 695 12 561 (2000-05-01), None
patent: 0 788 237 (1997-08-01), None
patent: WO 99/31805 (1999-06-01), None
“A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35- μm CMOS Technology,” Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvalison, Urs Voegeli and Zhenhua Wang, IEEE Journal of Solid-State Circuits, vol. 35, No. 7, Jul. 2000, pp. 1039-1045.
“CMOS High-Speed Dual-Modulus Frequency Divider for RF Frequency Synthesis,” Navid Foroudi and Tadeusz A. Kwasniewski, IEEE Journal of Solid-State Circuits, vol. 30, No. 2, Feb. 1995, pp. 93-100.
“A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, Jan Craninckx and Michael S. J. Steyaert, IEEE Journal of Solid-State Circuits, vol. 33, No. 12 Dec. 1998, pp. 2054-2065.
International Search Report, Int'l Application No. PCT/DE03/03423, Int'l Filing Date Oct. 15, 2003, 2 pgs.
Neurauter Burkhard
Scholz Markus
Callahan Timothy P.
Cox Cassandra
Eschweiler & Associates LLC
Infineon - Technologies AG
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