Frequency divider with variable modulo

Details Frequency divider with variable modulo Frequency divider with variable modulo

2000-04-03

2001-08-28

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

06282255

ABSTRACT:

The present invention relates to a variable-modulo frequency divider.
It applies in particular to constructions of frequency synthesizers with high spectral purity using variable-rank dividers operating at high frequencies with low modulos.
To construct dividers with low division ranks it is known practice to use commercial synchronous counters of the type for example of those marketed under the references 54163 and 10136 respectively by the companies registered in the United States TEXAS INSTRUMENTS and MOTOROLA or to use flip-flops linked in cascade according to the diagram of
FIG. 1
which is that of a divider with two modulos
4
and
5
or else according to diagrams adopted in integrated circuits of the type for example of that which is marketed under the reference SP8680 by the company registered in Britain General Electric Company, or else according to patent application JP-A-63-283316.
However, commercial counters and constructions of dividers by means of cascaded flip-flops exhibit limited operation within the high frequencies. This is mainly due, in constructions of the type of those of
FIG. 1
, to the presence of feedback logic gates which increase the propagation times of the signals between the outputs of the flip-flops and the feedback input of the first flip-flop.
Other types of construction of dividers of the type of that shown in
FIG. 2
, which is that of a divider with two modulos
4
and
5
, also implement cascaded flip-flops. However, unlike in the case of the model of
FIG. 1
, the feedbacks are not achieved by logic gates but by a hard-wired “OR” circuit constructed by simple connections between outputs of flip-flops and the D input of the first flip-flop making it possible to obviate the propagation times of the signals in the logic gates. This last type of construction makes it possible to obtain higher operating frequencies than the constructions described previously but has the drawback of being limited in the number of achievable division ranks, and in the possible combinations.


REFERENCES:
patent: 4443887 (1984-04-01), Shiramizu
patent: 4648103 (1987-03-01), Welty et al.
patent: 5172400 (1992-12-01), Maemura
patent: 6067339 (2000-05-01), Knapp et al.
Patent Abstracts of Japan, vol. 012, No. 469 (E-691), Dec. 8, 1988, JP 63 190424, Aug. 8, 1988.
Patent Abstracts of Japan, vol. 009, No. 075 (E-306), Apr. 4, 1985, JP 59 210729, Nov. 29, 1984.
Patent Abstracts of Japan, vol. 005, No. 171 (E-080), Oct. 30, 1981, JP 56 098030, Aug. 7, 1981.
Patent Abstracts of Japan, vol. 013, No. 113 (E-729), Mar. 17, 1989, JP 63 283316, Nov. 21, 1988.

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