Frequency divider with lower power consumption

Details Frequency divider with lower power consumption Frequency divider with lower power consumption

1998-09-15

2000-05-23

Callahan, Timothy P.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

327115, 327117, 377 48, H03K 2100

Patent

active

060673397

ABSTRACT:
A frequency divider such as a dual modulus prescaler has a division factor switchable between 1/N and 1/(N+1) and an input frequency of approximately 1 GHz as occurs, for example, in mobile telecommunication systems (GSM or DECT telephones). Low power consumption is achieved by using only the input flipflop to process the relatively high input frequency and an intermediate signal having only half the frequency is supplied to an intermediate divider and an output signal is already taken at a penultimate stage of a divider expansion connected following the intermediate divider.

REFERENCES:
patent: 4606059 (1986-08-01), Oida
"10GHz GaAs JFET Dual-Modulus Prescaler IC," Kasahara et al., Electronics Letters, vol. 25, No. 14, Jul. 6, 1989, pp. 889-890.
"A 1.75-Ghz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 .lambda.m CMOS," Craninckx et al., IEEE J. of Solid-State Circuits, vol. 31, No. 7, Jul., 1996, pp. 890-897.
Patent Abstracts of Japan, vol. 018, No. 270 (E-1552), May 23, 1994, for Japanese Application 04197982.
"A Sub-1 mA 1.5-GHz Silicon Bipolar Dual Modulus Prescaler," Seneff et al, IEEE J. of Solid-State Circuits, vol. 29, No. 10, Oct. 1994, pp. 1206-1211.
"A 3-mW 1.0-GHz Silicon-ECL Dual-Modulus Prescaler IC," Mizuno et al, IEEE J. of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1794-1798.
"Digitale Schaltungen," Seifart (1990), pp. 168-178.

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