Frequency divider presettable to fractional divisors

Details Frequency divider presettable to fractional divisors Frequency divider presettable to fractional divisors

1982-11-16

1985-01-15

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

364703, H03K 2136, G06F 768

Patent

active

044942435

ABSTRACT:
Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle. For arbitrary fractional divisors, the maximum phase-jitter amplitude is equal to the smallest adjustable time delay and, hence, considerably smaller than the clock period (T') of the signal to be divided (F).

REFERENCES:
patent: 3959737 (1976-05-01), Tanis
patent: 4241408 (1980-12-01), Gross
patent: 4295158 (1981-10-01), Nissen et al.
patent: 4423381 (1983-12-01), Stepp et al.

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