Frequency divider circuit with selectable integer/non-integer di

Details Frequency divider circuit with selectable integer/non-integer di Frequency divider circuit with selectable integer/non-integer di

1978-03-20

1980-03-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 42, 328 48, 307224C, 307225C, H03K 2136

Patent

active

041930371

ABSTRACT:
A divide circuit is provided for dividing an input signal of frequency N by the quantity M+0.5, where N is any positive number and M is an integer. In one embodiment a clock signal operating at a frequency of 3.5 megahertz is divided by 3.5, yielding an output signal of 1 megahertz. Additional logic means may be provided responsive to a control signal for dividing the input signal by the quantity M+1 for a given state of the control signal.

REFERENCES:
patent: 3456200 (1969-07-01), Bos
patent: 3614631 (1971-10-01), Bevier
patent: 3644834 (1972-02-01), Taylor et al.
patent: 3930169 (1975-12-01), Kuhn
patent: 3967205 (1976-06-01), Rossi et al.
patent: 4031476 (1977-06-01), Goldberg
patent: 4041403 (1977-08-01), Chiapparoli

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