Frequency divider circuit with integer and non-integer divisors

Details Frequency divider circuit with integer and non-integer divisors Frequency divider circuit with integer and non-integer divisors

1989-03-20

1990-06-19

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 52, 377 56, 377108, 377110, H03K 2348, H03K 2108

Patent

active

049359444

ABSTRACT:
A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state, and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to the output signals of the polynomial counter, implements a predetermined logical mapping of said output signals into a decoded output signal. The clock edge selector, responsive to the decoded output signal of the decode logic, utilizes flip-flops and other logic to generate integer and non-integer multiples of the clock signal. The frequency divider circuit selects either integer or non-integer divisors depending on the informational content of a control signal.

REFERENCES:
patent: 3896387 (1975-07-01), Kokado
patent: 3976946 (1976-08-01), Schroder
patent: 4031476 (1977-06-01), Goldberg
patent: 4041403 (1977-08-01), Chiapparoli, Jr.
patent: 4193037 (1980-03-01), Kyu
patent: 4295056 (1981-10-01), Luscher
patent: 4573176 (1986-02-01), Yeager
patent: 4587664 (1986-05-01), Iida
patent: 4658406 (1987-04-01), Pappas
patent: 4748347 (1988-05-01), Tung
patent: 4866741 (1989-09-01), Minuhin

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