Frequency divider circuit and digital PLL circuit

Details Frequency divider circuit and digital PLL circuit Frequency divider circuit and digital PLL circuit

1998-09-16

2000-12-19

Wambach, Margaret R.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327150, 327151, 327159, 377 44, 377 47, H03K 2100

Patent

active

061631817

ABSTRACT:
A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a reference clock signal and divides the input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal; a second circuit module which drives D-FFs connected in series using the first divided signal as a reference clock signal and divides the first divided signal by a frequency division ratio corresponding to the number of D-FFs connected in series to produce an output signal; and an OR circuit which produces a frequency division ratio determining signal based on the outputs of the D-FFs of the second circuit module and a frequency division ratio selecting signal.

REFERENCES:
patent: 4383303 (1983-05-01), Hoffman
patent: 4393301 (1983-07-01), Svendsen
patent: 5089717 (1992-02-01), Gamand et al.
patent: 5091699 (1992-02-01), Erickson et al.

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