Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Patent
1993-10-13
1995-01-24
Wambach, Margaret R.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
H03K 2100
Patent
active
053848160
ABSTRACT:
A programmable divide-by-N or divide-by-N+1/2 circuit is responsive to an input clock signal and to a plurality of binary-coded data signals corresponding to the divisor for providing an output clock signal having a frequency which is the frequency of the input clock signal divided by the value encoded on the data signals. The circuit includes two separate down counters 10, 12--one decrementing on the positive-going edge of the input clock signal and the other decrementing on the negative-going edge of the input clock signal.
If the divisor is an integer N, the negative-clocked circuitry 12 is disabled and the positive-clocked circuit 10 counts down from N to 1 continuously. If the divisor is N+1/2, both counter circuits are used. In this case, both counters are preset with the value N, the positive-edge-triggered counter 10 decrements from N to zero while the negative-edge-triggered counter 12 decrements from N to one. Then, both are preset with the value N, and this time the positive-edge-triggered counter 10 decrements to one while the negative-edge-triggered counter 12 decrements to zero. This count swapping occurs continuously. The resulting output signals are combined in a shaping circuit 14 to produce a frequency-divided output signal having a preselected low-state pulse width.
REFERENCES:
patent: 5214682 (1993-05-01), Clark
patent: 5224132 (1993-06-01), Goldberg
patent: 5235531 (1993-08-01), Foerg
DiMarco Matthew J.
Prysby Daniel G.
Brady III W. James
Donaldson Richard L.
Maginniss Christopher L.
Texas Instruments Incorporated
Wambach Margaret R.
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