Frequency divider and method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S118000

Reexamination Certificate

active

06229357

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronic systems using high frequency signals, and in particular, the present invention relates to frequency dividers.
BACKGROUND OF THE INVENTION
Frequency dividers are used in many electronic systems to produce signals having frequencies lower than those already existing. For example, if a 100 Megahertz (MHZ) signal exists in a system, but a 50 MHZ signal is desired, a frequency divider that divides the frequency by two can be employed.
FIG. 1
shows a prior art frequency divider that divides an input signal frequency by two. Prior art frequency divider
100
includes D-type flip flop
110
and inverter
115
. The input signal is applied to the clock input of D-type flip flop
110
, which transitions the logical state of the Q output to be equal to the logical state of the D input when the input signal transitions from low to high. Inverter
115
applies to the D input a signal that is opposite in logical state to the Q output, so that the Q output changes logical state in response to the rising edge of the input signal. This results in an output signal with a frequency that is one half of the input signal frequency.
Prior art frequency dividers have maximum operating frequencies, beyond which operation is not reliable. One problem with prior art frequency dividers is low maximum operating frequencies. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for alternate methods and apparatus for dividing the frequency of signals.
SUMMARY OF THE INVENTION
In one embodiment, a frequency divider is described. The frequency divider includes a pulse generator that has an input node coupled to an input of the frequency divider. The pulse generator also has an output node, and is configured to provide signal pulses on the output node. The frequency divider further includes a latch coupled to the output node of the pulse generator. The latch has a logical state, and is configured to change logical state in response to the signal pulses.
In another embodiment, a phase lock loop is described. The phase lock loop includes a phase comparator coupled to an input of the phase lock loop, an oscillator responsive to the phase comparator, and a frequency divider. The frequency divider includes a pulse generator and a latch, the latch being configured to change logical state in response to signal pulses produced by the pulse generator.
In another embodiment, an integrated circuit is described. The integrated circuit includes an input node configured to receive an input signal having a frequency and multiple periods, and also includes a frequency divider for dividing the frequency of the input signal. The frequency divider includes a pulse generator configured to produce a pulsed signal having one pulse for each of the periods, and also includes a latch having a logical state. The latch is configured to change the logical state in response to each pulse on the pulsed signal.
In another embodiment, a method of dividing the frequency of an input signal is described. The method includes detecting an edge of the input signal, producing a pulsed signal in response to the edge, and changing a logical state of a latch in response to the pulsed signal.


REFERENCES:
patent: 5111489 (1992-05-01), Tanaka et al.
patent: 5359232 (1994-10-01), Eitrheim et al.
patent: 5684418 (1997-11-01), Yanagiuchi
patent: 6031429 (2000-02-01), Shen

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