Frequency divider and associated methods

Details Frequency divider and associated methods Frequency divider and associated methods

2008-04-15

2008-04-15

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S115000, C377S047000, C377S048000

Reexamination Certificate

active

07358782

ABSTRACT:
The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz. A third embodiment includes the features of both the first embodiment and the second embodiment.

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Millman et al.,Microelectronics, McGraw-Hill, Inc. 1987, 2ndEdition, pp. 318-325 and 329-340.

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