Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
1999-06-29
2001-09-04
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S057000, C331S00100A, C377S047000, C327S156000, C327S115000, C327S117000
Reexamination Certificate
active
06285262
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a frequency divider, and particularly to a dynamic frequency divider comprising differential circuits. The present invention also relates to a phase lock oscillator using such a frequency divider. Further, the present invention relates to a flip-flop circuit obtained by improving the frequency divider.
A dynamic frequency divider, using differential circuits, is known as a frequency divider suitable for a high-speed operation.
FIG. 1
shows a conventional dynamic frequency divider, wherein a ring oscillator structure is made of two basic gates, each having a pair of emitter-coupled differential transistors, which constitute a differential circuit, and an emitter follower which receives outputs from the collectors of the transistors.
More specifically, a basic gate
1
of a first stage (first basic gate
1
) comprises a first pair of emitter-coupled differential transistors Q
1
and Q
2
, to which resistors R
1
and R
2
serving as collector loads are connected, and an emitter follower comprised of transistors Q
3
and Q
4
which receive collector outputs of the transistors Q
1
and Q
2
. Similarly, a basic gate
2
of a second stage (second basic gate
2
) comprises a second pair of emitter-coupled differential transistors Q
5
and Q
6
, to which resistors R
3
and R
4
serving as collector loads are connected, and an emitter follower comprised of transistors Q
7
and Q
8
which receive collector outputs of the transistors Q
5
and Q
6
.
Emitter outputs of the transistors Q
7
and Q
8
constituting the emitter follower of the second basic gate
2
are fed back to the bases of the emitter-coupled differential transistors Q
1
and Q
2
of the first basic gate
1
, so that the phase of a signal is inverted in one cycle.
The common emitter of the emitter-coupled differential transistors Q
1
and Q
2
of the first stage and the common emitter of the emitter-coupled differential transistors Q
5
and Q
6
are respectively connected to the collectors of a third pair of emitter-coupled differential transistors Q
9
and Q
10
. The common emitter of the emitter-coupled differential transistors Q
9
and Q
10
is connected to a current source CS
1
. The emitters of the transistors Q
3
, Q
4
, Q
7
and Q
8
constituting the emitter followers are individually connected to current sources CS
3
, CS
4
, CS
7
and CS
8
.
Differential input signals CK and /CK are input to the bases of the third pair of emitter-coupled differential transistors Q
9
and Q
10
. Frequency-divided output signals are obtained from outputs OUT and /OUT of the emitter follower (emitter outputs of the transistors Q
7
and Q
8
) of the second basic gate
2
.
FIG. 2
shows a characteristic of an input signal power sensitivity with respect to a division frequency (a frequency of an input signal to be divided) in the conventional dynamic frequency divider. Unlike the normal frequency divider, the dynamic frequency divider performs self-excited oscillation at a specific frequency, i.e., free-running frequency f
freerun
, even if an input signal power is not input. As shown in
FIG. 2
, the input signal power sensitivity is high at the free-running frequency f
freerun
. At the other frequencies, a high input signal power is required. In other words, the input signal power sensitivity is low in a frequency range other than the free-running frequency.
Therefore, to extend the range of the use frequency of the frequency divider, it is effective to vary the free-running frequency. For this reason, the conventional art employs a method of varying the free-running frequency by changing the current value of the current source CS
1
shown in FIG.
1
. According to this method, however, the amplitude of an output signal is changed depending on the current value of the current source CS
1
. In other words, the method is disadvantageous in that the amplitude of an output signal is changed depending on the division frequency. Thus, the method is not suitable for practical use.
Moreover, the maximum division frequency of the conventional dynamic frequency divider is ½ &tgr;d, which is substantially determined by a delay time &tgr;d per basic gate. Therefore, to increase the maximum division frequency, i.e., to realize a high-speed operation, it is important to reduce the delay time &tgr;d. The delay time &tgr;d is the sum of the minimum switching time of the pair of emitter-coupled differential transistors and the delay time of the emitter follower in one basic gate. Since these values are substantially determined by the performance of the transistors, reduction in the delay time &tgr;d is inevitably limited.
As described above, the conventional dynamic frequency divider has the following drawbacks. First, if the free-running frequency is varied to extend the range of the use frequency, the amplitude of an output signal is changed depending on the frequency. Secondly, reduction in the delay time is limited, since the maximum division frequency is substantially determined by a delay time per basic gate, and the delay time is the sum of the switching time of the pair of emitter-coupled differential transistors and the delay time of the emitter follower in the basic gate and determined by the performance of the transistors.
BRIEF SUMMARY OF THE INVENTION
A main object of the present invention is to provide a frequency divider in which the free-running frequency is varied without a considerable change in the amplitude of an output signal to extend the range of use frequency, and the signal delay time per basic gate is shortened to make a high-speed operation possible.
Another object of the present invention is to provide a frequency divider in which the signal delay time is further reduced to make the operation speed higher and the efficiency of utilizing the power source voltage is increased.
According to a first aspect of the present invention, there is provided a frequency divider comprising:
first and second basic gates, each including first and second differential circuits, an adder unit for adding outputs from the first and second differential circuits and a buffer circuit to which an output from the adder unit is input, wherein the adder units of the first and second basic gates receive negative feedback from outputs from the adder units of the first and second basic gates by the second differential circuits of the first and second basic gates through the buffer circuits of the first and second basic gates, an output from the adder unit of the first basic gate is connected to an input of the first differential circuit of the second basic gate, and an output from the adder unit of the second basic gate is fed back to an input of the first differential circuit of the first basic gate;
a first current source for supplying a current in common to the first differential circuits of the first and second basic gates;
a first current switching circuit inserted between the first current source and the first differential circuits of the first and second basic gates; and
second and third current sources for respectively supplying currents to the second differential circuits of the first and second basic gates,
wherein a differential input signal is input to the first current switching circuit and a frequency-divided output signal is obtained from the buffer circuit of the second basic gate.
In the frequency divider thus constructed, the free-running frequency of the frequency divider is considerably changed by controlling the current (average current I
1
) supplied from the common current source through the current switching circuit to the first differential circuits of the first and second basic gates and the current (I
2
=I
3
=I
4
) supplied from the second and third current sources to the second differential circuits of the first and second basic gates. In this case, if the average of the squares of the values of the currents I
1
and I
2
is kept constant, an output signal amplitude can be kept constant.
Further, when the current I2 is increased, the amount of n
Kabushiki Kaisha Toshiba
Kinkead Arnold
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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