Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Comparing counts
Patent
1986-06-13
1987-11-03
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Comparing counts
377 48, 377 49, G06F 702, H03K 2366
Patent
active
047047232
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
The invention relates to a method and apparatus for achieving in a computer an optional division of a clock frequency C1 in a ratio A/B, where the quotient between B and A is a whole number C and a remainder D.
BACKGROUND
In a synchronous operation (e.g., between computer systems or between input/output means in digital telephone exchanges,) a timing accuracy of better than plus/minus 0.5% or is required, where the clock pulse frequency in the transmission of data may vary from 64 kHz to 1200 Hz. Particularly with high clock pulse frequencies, there is a problem when data is received by a computer for processing and distribution, this being to keep a constant data output flow within given accuracy limits for a continuous data input flow.
It is known to use a buffer store, where outgoing data are stored for transmission at a rate dependent on the space occupied in the buffer store. It is also known, with D/A signal conversion, to control a voltage-controlled oscillator depending on the degree of occupation in the buffer store, and subsequently to achieve frequency variations within the permitted plus or minus 0.5% via controllable division of the oscillator frequency. The method, however, requires a complicated circuit structure.
SUMMARY OF INVENTION
It is an object of the present invention to provide a method and an apparatus with the aid of which an optional division of the internal clock frequency of a computer may be effected in an easily integratable way in a system.
In achieving the above and other objects and advantages of the invention, there is provided an apparatus for dividing a clock frequency C1 according to a ratio A/B, where the quotient between B and A is a whole number C and a remainder D, and where a limited deviation in the pulse length of the divided frequency is permitted. In this apparatus, the clock pulses C1 include two half pulses equal in length to one another.
The aforesaid apparatus comprises first and second counters for generating counts, a bistable multivibrator, and first and second switches. The apparatus moreover comprises a first register for registering the number C, a second register for registering numbers A-D, and a third register for registering the number D. Also included is a divider which includes a first comparator circuit which receives the number registered in the first register and the count from the first counter.
The apparatus moreover includes a clock generating a clock signal at the frequency C1, the first counter being stepped forward one step for each half pulse of the clock signal having frequency C1 until it has reached the value of the number in the first register. The comparator circuit then sends a signal resetting the bistable multivibrator and also setting the first counter to zero, a signal being generated for stepping forward the second counter. The divider includes a second comparator circuit which receives the count from the second counter and also receives the number in the second register. When there is equality, this causes the second comparator circuit to send a signal which sets the second counter to zero and resets the first switch which then adds the number "1" to the number in the first register before connection to the first comparator takes place. It also resets the second switch to connect the third register instead of the second register to the second comparator circuit.
The method of the invention has to do with the above-stated relationship according to ratio A/B where the quotient of B and A is a whole number C and a remainder D. This method comprises storing C, A-D and D. It further comprises a sequence of counting the half pulses of the clock pulses to obtain a count which is compared to C and generating a first signal when the count equals C. Further included is the counting of the number of times the first signal is generated and comparing the resulting count with A-D and generating a second signal when the second said count equals A-D. C is then varied by 1 and D is compared with the number of times
REFERENCES:
patent: 3829664 (1974-08-01), Kashio
patent: 4318046 (1982-03-01), Sonntag
patent: 4468796 (1984-08-01), Suga
Heyman John S.
Telefonaktiebolaget LM Ericsson
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