Frequency divider

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override

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Details

327556, 327558, 327311, 327320, 327532, 327117, 377 47, H03K 500, H03K 2102

Patent

active

057291705

ABSTRACT:
An input buffer circuit for a frequency divider includes a bias circuit including a first group of diodes connected in series and to a power supply voltage terminal, at least first and second resistors connected in series to each other at a first junction, the first resistor being connected in series with the first plurality of diodes, and a second plurality of diodes connected in series, the second plurality of diodes being connected between the second resistor and a ground; an input signal terminal for receiving an input signal from a frequency divider; a reference input terminal for receiving a reference signal; an output signal terminal; a reference output terminal connected to the reference input terminal; an amplitude limiting circuit connected to and between the output signal terminal and the reference output terminal; third and fourth resistors connected in series to each other at a second junction, the third resistor being connected to the output signal terminal and the fourth resistor being connected to the reference output terminal, the first and second junctions being connected together; and a capacitor connecting the first and second junctions to ground.

REFERENCES:
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patent: 4438405 (1984-03-01), Yazawa et al.
patent: 4633520 (1986-12-01), Okazaki
patent: 4638180 (1987-01-01), Sagawa et al.
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patent: 4749951 (1988-06-01), Tanaka
patent: 5130579 (1992-07-01), Thomas
patent: 5214681 (1993-05-01), Satoh
Maemura et al, "A 1GHz-2mA/5V GaAs 128/129 Prescaler IC", Proceedings of the IEEE GaAs IC--Gallium Arsenide Integrated Circuit Symposium, Oct. 1987, pp. 273-276.

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