Frequency detector for a phase locked loop system

Details Frequency detector for a phase locked loop system Frequency detector for a phase locked loop system

2002-03-15

2003-11-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

C327S042000

Reexamination Certificate

active

06642747

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to phase locked loops. More particularly, the present invention is related to a frequency detector that may be used in a phase locked loop system to acquire a frequency lock.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) circuits are useful in many electronic systems. Example application for PLL circuits include master clock generation for a microprocessor system, clock generation for a sampling clock in an analog-to-digital conversion system, clock generation for data recovery in a low-voltage differential signal (LVDS) driver/receiver system, as well as numerous other applications.
PLL applications typically provide an output clock signal by comparing the output clock signal to a reference clock signal. A phase-frequency detector (PFD) circuit is often employed to provide a raw control signal to a loop filter. The phase-frequency detector circuit provides the raw control signal in response to comparing the phase and frequency of the output clock signal to the reference clock signal. The loop filter often is a low-pass filter (LPF) that is arranged to provide a smoothed or averaged control signal in response to raw control signal. A voltage-controlled oscillator (VCO) is arranged to receive the control signal from the loop filter. The VCO produces the clock signal in response to the control signal such that the frequency of the clock is varied until the phase and frequency of the clock signal are matched to the reference clock signal.
One example PLL circuit includes a PFD circuit that provides UP and DOWN signals in response to the comparison between the output clock signal and the reference clock signal. The UP signal is active when the frequency of the output clock signal is low, while the DOWN signal is active when the frequency of the output clock signal is determined to be high. Similarly, the UP signal is active when the phase of the output clock is lagging behind the phase of the reference clock, and the DOWN signal is active when the phase of the output clock is leading the phase of the reference clock.
SUMMARY OF THE INVENTION
A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.
According to one example, the frequency detector is useful in a frequency locked loop application. The frequency detector compares the frequency between a reference clock signal and another clock signal, without comparing the phase of the signals. The frequency detector provides UP and DOWN signal that indicate the difference in the reference clocks signal and the other clock signal. At steady-state, the UP and DOWN signals stabilize at a fixed logic level (i.e., a low logic level) when the frequency of the reference clock signal and the other clock signal are locked with respect to one another. The frequency locked relationship between the reference clock signal and the other clock signal is independent of any phase relationship between the signals.
According to another example, a frequency detector is arranged to drive a charge pump circuit with UP and DOWN signals. The charge pump circuit provides a control signal to a voltage-controlled oscillator such that a VCO clock signal is produced. The UP and DOWN signals stabilize to a common logic level (i.e. a low logic level) when the frequency of the VCO clock signal is locked to the frequency of a reference clock signal. A phase-detector that is separate from the frequency detector may be employed to adjust the phase relationship between the VCO clock signal and the reference clock signal. The frequency detector operates without detecting (or comparing) the phase relationship between the reference clock signal and the VCO clock signal.


REFERENCES:
patent: 6100721 (2000-08-01), Durec et al.
patent: 6133797 (2000-10-01), Lovelace et al.
patent: 6407642 (2002-06-01), Dosho et al.
patent: 6483387 (2002-11-01), Fernandez-Texon
Messerschmitt, “Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery,” reprinted fromIEEE Trans. Comm., vol. COM-27, pp. 1288-1295, Sep. 1979, pp. 107-114.

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