Frequency detector detecting variation in frequency...

Details Frequency detector detecting variation in frequency... Frequency detector detecting variation in frequency...

2005-11-01

2005-11-01

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S00100A, C331S025000, C327S159000, C327S043000, C327S012000, C375S376000

Reexamination Certificate

active

06960960

ABSTRACT:
A reference clock signal or a clock signal delayed in phase from the clock signal by π/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.

REFERENCES:
patent: 6055286 (2000-04-01), Wu et al.
patent: 6366135 (2002-04-01), Dalmia et al.
patent: 11-308097 (1999-11-01), None
“WA 20.5 A 1Gb/s CMOS Clock and Data Recovery Circuit”, Hui Wang et al., ISSCC Digest of Technical Papers, Feb. 1999.

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