Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2001-03-26
2002-03-26
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S025000, C331S027000, C327S042000, C327S048000
Reexamination Certificate
active
06362693
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a frequency detection method for adjusting the clock signal frequency of a local oscillator to the data rate of a received binary data signal. The invention also relates to a frequency detector circuit for carrying out the method.
For synchronizing clock signals, a PLL (phase locked loop) is frequently used in which the clock signal phase of a local oscillator is compared by a phase detector with the phase position of the received data signal and is adjusted. Because a phase locked loop does not lock if the frequency of the local oscillator differs too greatly from the data rate, a frequency comparison, by means of which the oscillator frequency is pretuned, must also be carried out.
A method which is known in this context, and which is described in the paper by A. Pottbäcker et al: “A Si Bipolar Phase And Frequency Detector IC For Clock Extraction Up To 8 Gb/s” in “IEEE J. Sol.-State circuits”, Vol. 27, No. 12, December 1992, pp 1747-1751 and in the paper by D. G. Messerschmitt: “Frequency Detectors For PLL Acquisition In Timing And Carrier Recovery” in “IEEE Trans. Comm. Vol. COM-27, No. 9, September 1979, pp 1288-1295, is to use sequential circuits, for example of the rotation frequency detector, which samples a normal and a quadrature signal clock, i.e. a signal clock delayed by 90°, with the data signal in order to acquire the frequency information.
Because received data signals are usually subject to more or less severe jitter, this method is in practice suitable only to a certain degree. When the jitter is severe, the frequency detector supplies incorrect information and can disrupt the clock signal synchronization even after the locking process has already occurred.
In order to avoid this problem, in other approaches, a reference signal with quartz precision is used, with which signal the local oscillator is tuned into the locking-in range of the phase locked loop. The disadvantage of this method, which is known, for example, from the paper by Sam Yinshang Sun: “A High Speed High Jitter Tolerant Clock And Data Recovery Circuit Using Crystal Based Dual PLL” in “IEEE 1991 Bipolar Circuits And Technology Meeting”, pp 293-296, is that a reference signal has to be supplied or generated with a quartz.
BRIEF DESCRIPTION OF THE DRAWINGS
It is accordingly an object of the invention to provide a frequency detector circuit and a frequency detection method for adjusting the clock signal of a local oscillator to the data rate of a received binary signal which overcomes the above-mentioned disadvantages of the prior art circuits and methods of this general type. In particular, it is an object of the invention to provide a method and a circuit to reliably compare the data rate of a received data signal and the clock signal frequency of a local oscillator without disruption even when there is severe jitter on the received data signal, and without having to generate a reference signal which has quartz precision with a quartz.
With the foregoing and other objects in view there is provided, in accordance with the invention a frequency detection method for adjusting a clock signal frequency of a local oscillator to a data rate of a received binary data signal with a signal edge change probability of {fraction (1/2+L )}. The method includes steps of: obtaining a clock signal having a frequency from a local oscillator; frequency dividing the clock signal by a first division factor of 4 to obtain a first frequency divided clock signal; frequency dividing the first frequency divided clock signal by a second division factor to obtain a second frequency divided clock signal, and frequency dividing a received data signal by the second division factor to obtain a frequency divided data signal (the received data signal and the frequency divided clock signal are divided by the same division factor); determining a frequency of the second frequency divided clock signal and determining a frequency of the frequency divided data signal by running counting processes simultaneously in parallel in counters which provide two counter signals; in a subtractor, comparing the frequency of the second frequency divided clock signal with the frequency of the frequency divided data signal by obtaining a difference between the two counter signals; converting the difference obtained by the subtractor into an analog output signal; and using the analog output signal to control the frequency of the clock signal of the local oscillator.
In transmission systems, the user information is usually scrambled because this is a way of improving the spectral properties of the data signal for the transmission. The probability that the state of a data signal bit will change at a possible time is {fraction (1/2+L )} in this case. This property is used in the method according to the invention and exploited in order to obtain frequency information.
A reset signal, which resets the counters operating in parallel and avoids an overflow at the subtractor, is advantageously derived from the final reading of the subtractor.
In accordance with an added feature of the invention, after frequency adjustment of the clock signal of the local oscillator has taken place, the clock signal phase of the local oscillator is compared with the phase position of the received data signal by means of a PLL (phase locked loop) provided with a phase detector and a loop low-pass filter and adjusted. The analog output signal is fed to the loop low-pass filter in the PLL via an adder during the frequency adjustment, as a result of which the clock signal frequency of the local oscillator is modified until it has adjusted to the data rate of the received data signal.
When the PLL locks, a lock signal, which is fed as a reset signal to the counters operating in parallel is then advantageously derived, with the result that the frequency controlling process is terminated. The PLL then starts its phase control operation.
In accordance with an additional feature of the invention, after a specified number of clock signal pulses, a reset pulse which resets the counters operating in parallel, with the result that the frequency control process is switched off, is output by a counter designated as a plesiochronous counter.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a frequency detector circuit that includes a clock signal path for dividing a frequency of a clock signal applied to the clock signal path from a local oscillator. The clock signal path includes, in series, a 1:4 frequency divider, then a precounter, and finally a ring counter having an output providing a counting value. A data signal path is provided for dividing a frequency of a received binary data signal. The data signal path includes, in series, a precounter that is identical to the precounter in the clock signal path, and a ring counter having an output providing a counting value. The ring counter in the data signal path is identical to the ring counter in the clock signal path. A subtractor has a first input connected to the output of the ring counter in the clock signal path and a second input connected to the output of the ring counter in the data signal path. The subtractor outputs a difference between the counting value output by the ring counter in the clock signal path and the counting value output by the ring counter in the data signal path. A digital to analog converter receives the difference from the subtractor and converts the difference into an analog output signal for controlling the frequency of the clock signal of the local oscillator.
Here, a 1:2-frequency divider is expediently connected in each case between the precounter and the ring counter both in the clock signal path and in the data signal path.
The subtractor is advantageously designed in such a way that it also forms the difference between the counting values at its two inputs beyond the overflow limits of the ring counter. In addition, the subtractor also has a further output at which a reset si
Grimm Siegfried H.
Infineon - Technologies AG
LandOfFree
Frequency detection method for adjusting a clock signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency detection method for adjusting a clock signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency detection method for adjusting a clock signal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2871029