Frequency controlled reference clock generator

Details Frequency controlled reference clock generator Frequency controlled reference clock generator

1995-03-06

1996-07-09

Psitos, Aristotelis

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

331 25, 327159, 327160, G11B 2732

Patent

active

055350674

ABSTRACT:
The invention is a write clock generator circuit adapted for use in disk drives having either dedicated servo or sector servo architecture. A high frequency write clock signal is generated from a relatively low frequency reference signal synchronized to disk rotation. The reference signal may originate from a number of sources, including a dedicated servo pattern, a sector servo pattern, any index pattern, or a spindle pulse. A clock generates a clock signal having a predetermined number of cycles for each reference period. A counter coupled to the output of the clock counts the number of clock cycles generated for each reference period. The number of cycles is then compared to an expected number corresponding to a desired clock frequency. If the compared numbers are not the same, an error signal is generated. Control logic receives the error signal and the reference signal, and generates an appropriate control signal. The control signal is coupled to the clock and thereby adjusts the write clock signal frequency.

REFERENCES:
patent: 4862485 (1989-08-01), Guinea et al.
patent: 5121280 (1992-06-01), King
patent: 5146183 (1992-09-01), Wilson
patent: 5218491 (1993-06-01), Nishida et al.
patent: 5309418 (1994-05-01), Suzuki
Paul R. Gray and Robert G. Meyer, "Analysis and Design of Analog Integrated Circuits, 2nd Edition," date unknown, pp. 615-616.

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