Frequency-controlled DLL bias

Details Frequency-controlled DLL bias Frequency-controlled DLL bias

2006-12-05

2006-12-05

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S050000, C327S162000

Reexamination Certificate

active

07145373

ABSTRACT:
A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitude to a reference signal. The comparator then generates a tail current control signal for the DLL based on a result of the comparison. In one embodiment, the reference signal is indicative of a predetermined tail current value for the DLL, and the tail current control signal adjusts delay of the DLL to equal the predetermined tail current value. Preferably, the tail current control signal maintains the DLL signal output at a substantially constant amplitude in spite of frequency variations and may also be used to set the voltage swing for the DLL.

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D.A. Johns and K. Martin, Analog Integrated Circuit Design, pp. 21-25 (1997).

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