Pulse or digital communications – Synchronizers
Reexamination Certificate
1998-01-22
2001-07-24
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
C375S372000, C375S373000, C375S375000, C369S059160
Reexamination Certificate
active
06266381
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a frequency control arrangement and more particularly, though not exclusively, to a frequency control arrangement suitable for use in a wideband phase locked loop.
Wideband phase locked loops are widely used in the extraction of data from CD-ROMs and digital video data (DVD) ROMs They are essentially used to generate a clock signal which is synchronous with an incoming efm data signal and to output the clock signal with the efm data signal.
Efm data is required to contain a maximum mark or space at least once in a specified number of data intervals. In the case of CD-ROM. the efm data is required to contain a maximum mark or space of 11 T every 588 written T intervals. DVD-ROM efm data is required to contain a maximum mark or space of 14 T every 1488 written T intervals. This requirement of the efm data allows detector circuitry to be synchronised to the efm data stream by allowing the frequency of the efm data stream to be detected.
This frequency detection is performed digitally by measuring the maximum mark or space but the resolution of the measurement is limited by the clock frequency of the frequency detector circuit. It is not generally possible to increase the clock frequency because the clock signal is output to data recovery circuitry as being synchronous with the incoming efm data stream.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a frequency control arrangement comprising an oscillator, a mark or space counter, a frequency detector and an error signal calculator in which it is desired to control the oscillator to resonate at a frequency substantially equal to the frequency of a received data stream, the oscillator being a ring oscillator which is arranged to provide phased clock signals on respective output lines to the mark or space counter thereby to allow the mark or space counter to measure the length of the marks or spaces of the data with increased resolution.
In accordance with another aspect of the present invention there is provided a frequency control arrangement for controlling an oscillator to operate at a frequency substantially equal to the clock frequency of a received stream of data signals, wherein the oscillator is a ring oscillator which is arranged to provide a plurality of clock signals of different phases on respective output lines to a mark or space counter to clock into said counter the instantaneous value of said data signals at a like plurality of intervals within a cycle of said clock frequency.
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Chin Stephen
Liu Shnwang
LSI Logic Corporation
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