Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By frequency
Reexamination Certificate
2001-05-30
2003-06-17
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By frequency
C327S040000
Reexamination Certificate
active
06580297
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the technical field of data reproduction devices that reproduce data stored on a recording medium while the disk-shaped recording medium, e.g., an optical disk, such as a CD (compact disc) or a DVD (digital video disc), is rotated at constant speed.
BACKGROUND OF THE INVENTION
Modulated data with a prescribed number of bits in which the original digital data have been EFM modulated are stored on disk-shaped recording media (hereafter called discs), e.g., CDs or DVDs. To demodulate and reproduce these modulated data, a motor is driven, and while the disk is rotated at constant speed, an optical pickup is moved to a read position. In the read position, the optical pickup illuminates the rotating disc, the light reflected by the disc is sensed, and analog RF (radio frequency) signals that indicate the stored contents of the disc are produced.
On discs, e.g., DVDs, data are described with a CLV (constant linear velocity) system, that is, a system that maintains a constant linear speed, and reading devices often read with a CAV (constant angular velocity) system, where the angular velocity is constant, since disc rotation is easily controlled. In such cases, the read frequency of RF signals varies according to the disc read position. The RF signals are read synchronized to reference clocks, so that when the reference clock frequency is fixed, they cannot be synchronized to the RF signals and they cannot be read correctly.
In order to read the RF signals correctly, reference clock frequency must be constantly controlled to agree with the RF signal read frequency.
Letting the time corresponding to 1 bit of data be T, with DVDs, RF signals are data that have a maximum 14T pulse width, and a period of 1488T is considered one frame. One frame contains only one pulse string that has a pulse width of 14T and it is used as the frame synchronizing signal.
To reproduce reference clocks from such RF signals, the reference clock frequency must first be matched to the RF signal read frequency. For this reason, the reference clock frequency is controlled so that a number (here
14
) that indicates the frame synchronizing signal period and the same number of reference clocks are output while frame synchronizing signals are output.
PLLs are often used as circuits for matching reference clock frequency and RF signal frequency. PLLs have a frequency comparison circuit, a loop filter with the input terminal connected to the output terminal of the frequency comparison circuit, and VCO (voltage-controlled oscillator) with the input terminal connected to the output terminal of the loop filter. They are constituted so that VCO output signals and RF signals will be input to the frequency comparison circuit. The frequency comparison circuit controls the VCO control voltage with RF signals as reference signals so that VCO output signal frequency and RF signal frequency will agree.
An example of a frequency comparison circuit that is used when reference clocks are produced from the RF signals of a DVD is indicated by reference number (
101
) in FIG.
7
.
This frequency comparison circuit (
101
) has edge detection circuit (
102
), counter (
103
), comparator (
104
), maximum latch circuit (
105
), minimum latch circuit (
106
), and timing generation circuit (
107
).
RF signals and reference clocks for when RF signals are read are input to edge detection circuit (
102
), the rising/falling edge of the RF signals is detected synchronized to the reference clock that is currently being output, and detection pulses are output to counter (
103
).
RF signal rising/falling edge detection pulses and reference clocks are input to counter (
103
) and the number of reference clock pulses are counted in binary values during the period from when the edge detection pulse is input until the next edge detection pulse is input. The count value is output to comparator (
104
).
Comparator (
104
) compares the output value of counter (
103
) with a number (here
14
) that indicates the frame synchronizing signal period and outputs the result to maximum latch circuit (
105
). When the output value of counter (
103
) is larger than the reference value “large” is output, when it is smaller, “small” is output, and when it is equal to the reference value, “equal” is output to maximum latch circuit (
105
).
Maximum latch circuit (
105
) compares the current value in the latch with the output of comparator (
104
), and the current value is replaced with a larger value. The priority for rewriting is “large,” “agree,” and “small.” When “small” is held and “equal” is input, it is replaced by “agree,” and when “equal” is held and “large” is input, it is replaced by “large.” And when “equal” is held and “small” is input, “equal” is held, and when “large” is held and “equal” or “small” is input, “large” is held.
With the aforementioned circuit, each time that an RF signal edge detection pulse is output sequentially by edge detection circuit (
102
), the number of reference clock pulses is counted by counter (
103
). This number of pulses corresponds to the RF signal pulse width. With comparator (
104
), each time that a count value is output from counter (
103
), the count value and a number that indicates the frame synchronizing signal period are compared and the comparison result is output to maximum latch circuit (
105
).
The value held in maximum latch circuit (
105
) is reloaded each time that a comparison result is input. This held value is reset by timing generation circuit (
107
) at time intervals that include at least one frame. Immediately before it is reset, the value held by maximum latch circuit (
105
) will be equal to the result of comparing the maximum value of the pulse width actually detected during one frame and a number that indicates the frame synchronizing signal period. The held value obtained in this way is output to minimum latch circuit (
106
).
Minimum latch circuit (
106
) compares the current value held in the latch with the output value of maximum latch circuit (
105
), and the current value is replaced with a smaller value. The priority for rewriting is “small,” “agree,” and “large.” When “large” is held and “equal” is input, “equal” is held, and when “equal” is held and “small” is input, “small” is held. When “equal” is held, if “large” is input, “equal” is held, and when “small” is held, if “equal” or “large”is input, “small” is held.
The value held by minimum latch circuit (
106
) is reset at time intervals that include multiple frames by timing generation circuit (
107
). During the period before reset, the results of comparing the maximum value of the pulse width actually detected in one frame and a number that indicates the frame synchronizing signal period are input multiple times from maximum latch circuit (
105
). Minimum latch circuit (
106
) holds the comparison result that corresponds to the smallest of those values.
As described above, one of the values “large, “agree,” or “small,” corresponding to the result of comparing the maximum value of the pulse width detected during one frame and a number that indicates the frame synchronizing signal period, is held by minimum latch circuit (
106
) and is output to a VCO; not shown, via a loop filter.
The VCO controls the reference clock frequency in response to the output value from minimum latch circuit (
106
). If the output value from minimum latch circuit (
106
) is “small,” the reference clock frequency is lower than the RF signal read frequency. Thus, the reference clock frequency is raised by a prescribed amount. On the other hand, if the output from minimum latch circuit (
106
) is “large,” the reference clock frequency is higher than the RF signal read frequency. Thus, the reference clock frequency is lowered to 7 a prescribed amount. By controlling the reference clock frequency in this way, the maximum value of the pulse width detected in one frame and a number that indicates the frame synchronizing signal period will agree.
The output value from minimum latch circuit (
106
) will be “equ
Brady W. James
Callahan Timothy P.
Kempler William B.
Nguyen Linh
Telecky , Jr. Frederick J.
LandOfFree
Frequency comparison circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency comparison circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency comparison circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3102118