Frequency comparator and PLL circuit using the same

Details Frequency comparator and PLL circuit using the same Frequency comparator and PLL circuit using the same

1999-04-19

2001-04-17

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C375S360000, C375S376000, C360S041000

Reexamination Certificate

active

06218907

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a frequency comparator and a PLL (phase locked loop) circuit using the frequency comparator, and more particularly relates to a PLL circuit which synchronizes with NRZ (non return to zero) signal and a frequency comparator which is suitably used for the PLL circuit.
2. Description of Related Art
A conventional PLL circuit which synchronizes with NRZ signal employs a structure which compares the oscillation clock of a voltage control oscillator (VCO) with the outside reference clock frequency which synchronizes with NRZ signal for comparing the frequency. An exemplary circuit of a PLL circuit is shown in FIG.
5
.
In
FIG. 5
, the oscillation clock of a voltage control oscillator
101
is served as one input to a phase comparator (PD)
102
and is served also as one input to a frequency phase comparator (PFD)
104
after the oscillation clock is divided into 1
(n denotes a natural number) by a frequency divider
103
. The phase comparator receives NRZ signal as the other signal, compares the phase of the oscillation clock of the voltage control oscillator
101
with that of the NRZ signal, and generates an UP signal for advancing the phase or a DOWN signal for delaying the phase based on the resultant phase difference.
On the other hand, the frequency phase comparator
104
receives a reference clock which synchronizes with NRZ signal as the other input, compares the 1
divided oscillation clock of the voltage control oscillator
101
with the frequency of the reference clock, and generates an UP signal for increasing the frequency or a DOWN signal for decreasing the frequency based on the phase difference.
The respective two outputs of the phase comparator
102
and the frequency phase comparator
104
enter to a selector
105
. The selector
105
selects one of two comparison outputs of the phase comparator
102
and the frequency phase comparator
104
based on a switching signal given by an external circuit (not shown in the drawing). The comparison output selected by the selector is supplied to the voltage control oscillator
101
through a charge pump circuit
106
and a loop filter
107
as a control voltage.
In the PLL circuit having the structure described herein above, first the selector
105
is switched to the frequency phase comparator
104
side, the frequency that is 1
clock of the oscillation clock of the voltage control oscillator
101
is drawn to the frequency near to the reference clock based on the comparison output of the frequency phase comparator
104
. After drawing, by giving a switching signal from an external circuit to the selector
105
, the selector
105
is switched to the phase comparator
102
side. The oscillation clock of the voltage control oscillator
101
is phase-synchronized with NRZ signal based on the comparison output of the phase comparator
102
.
The conventional PLL circuit needs a circuit for generating a reference clock which synchronizes with NRZ signal, and also needs an external circuit which detects drawing of 1
clock frequency of the VCO clock to the frequency near to the reference clock and generates a switching signal to switch the selector
105
, and such structure leads to a complex circuit structure. Further, a large loop gain of the phase comparator
102
is needed, and the large loop gain results in poor PLL transfer performance.
A PLL circuit having the structure which compares the phase with only NRZ signal without a reference clock which synchronizes with NRZ signal has been known, which PLL circuit has been developed to solve the problem described herein above. An exemplary circuit of such PLL circuit is shown in FIG.
6
. In
FIG. 6
, an oscillation clock of a voltage control oscillator (VCO)
11
enters to one terminal of a phase comparator (PD)
112
and a frequency comparator (FD)
113
respectively. NRZ signal enters to the other terminal of the phase comparator
112
and frequency comparator
113
.
The phase comparator
112
compares the phase of an oscillation clock of the voltage control oscillator
111
and NRZ signal, and generates an UP signal for advancing the phase or a DOWN signal for delaying the phase based on the resultant phase difference. The comparison output of the phase comparator
112
is supplied to the voltage control oscillator
111
through a charge pump circuit
114
and a loop filter
115
as a control voltage for controlling the phase.
On the other hand, the frequency comparator
113
compares an oscillation clock of the voltage control oscillator
111
with a frequency of NRZ signal, and generates an UP signal for increasing the frequency or a DOWN signal for decreasing the frequency based on the resultant frequency difference. The comparison output of the frequency comparator
113
is supplied to the voltage control oscillator
111
through the charge pump circuit
116
and the loop filter
117
as a control voltage for controlling the frequency.
FIG. 7
shows a conventional example of a circuit structure of the frequency comparator
113
. NRZ signal, an oscillation clock of the voltage control oscillator
111
shown in
FIG. 6
, namely VCO clock, CLK, a clock ICLK having the same phase as that of the VCO clock, and a clock QCLK having the phase which delays 90 degrees from that of the clock ICLK are supplied respectively to the conventional circuit.
In
FIG. 7
, NRZ signal enters to a D-flip-flop (referred to as D-FF hereinafter)
121
as D(data) input and also enters to one terminal of an exclusive-OR (referred to as EX-OR hereinafter) gate
122
. D-FF
121
receives a VCO clock as a CK (clock) input. A positive phase output Q of the D-FF
121
enters to the other terminal of the EX-OR gate
122
.
The clocks ICLK and QCLK enter to one terminal of respective AND gates
123
and
124
. The clock ICLK side input of the AND gate
124
is a negative logic input. The respective outputs of these AND gates
123
and
124
are supplied to D-FF's
125
and
126
as a D-input. The D-FF's
125
and
126
receives an output of the EX-OR gate
122
as a CK input.
Respective positive phase outputs Q of the respective D-FF's
125
and
126
enter to subsequent D-FF
127
and
128
as a D-input, and enter to one terminal of respective AND gates
131
and
132
. These D-FF's
127
,
128
,
129
, and
130
receive the VCO clock CLK as the CK input.
Positive phase outputs Q of the D-FF's
129
and
130
enter to the other terminal of the respective AND gates
131
and
132
. An output of the AND gate
131
is generated as a DOWN signal for decreasing the frequency and an output of the AND gate
132
is generated as an UP signal for increasing the frequency.
Next, the circuit operation of the frequency comparator having the structure described herein above is described with reference to a timing chart shown in FIG.
8
. In the timing chart shown in
FIG. 8
, an output of the AND gate
124
is denoted by (b), an output of the EX-OR gate
122
is denoted by (c), and the same corresponding components as shown in
FIG. 7
are given the same characters shown in FIG.
7
.
The output (a) of the AND gate
123
is in “H” level when the clock ICLK and QCLK are both in high level (referred to as “H” level hereinafter), the output (b) of the AND gate
124
is in “H” level when the clock ICLK is in low level (referred to as “L” level hereinafter) and the clock QCLK is in “H” level. The interval while the output (a) of the AND gate
123
is in “H” level is denoted by X, and the interval while the output (b) of the AND gate
124
is in “H” level is denoted by Y.
In a time period of the clock CLK that is the output of the VCO, when a data change of NRZ signal occurs in an interval X as shown in the timing chart in
FIG. 8
, the data change is detected by the D-FF
121
and the EX-OR gate
122
, and the output (c) of the EX-OR gate
122
changes to “H” level.
At that time, because the output (a) of the AND gate
123
is in “H” level, the output (a) is latched by the D-FF
125
at the transition timing of th

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