Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2001-05-04
2004-12-07
Lee, Michael H. (Department: 2614)
Television
Synchronization
Automatic phase or frequency control
C348S537000
Reexamination Certificate
active
06829014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to signal encoding and decoding, and more particularly to a system for controlling an oscillator used to decode and/or reconstruct a video signal.
2. Description of the Related Art
Modern video equipment including televisions, video cassette recorders VCRs, and set-top terminals provide users with tremendous access to television programming. In particular, cable and satellite television systems may provide access to hundreds of channels of video programming. A set-top terminal is a box of electronic circuitry connected between a user's television and a cable or satellite television system for assisting the user in accessing that system.
As the equipment for providing video programming becomes more complicated and offers more features and flexibility to users, the sophistication and programming required to operate such equipment also increases. In fact, some video equipment, particularly VCRs and set-top terminals, now require substantial computing power to optimally process video and audio signals and provide user features such as timed program recording and premium channel de-scrambling.
In general, to generate a visual display on a display device, such as a television set or monitor, the information for the images to be displayed must be provided as a video signal. This is also true of an on-screen display that is derived from a video signal generated by the video equipment. Conversion of a video signal into a visual image on a display screen requires the use of a clock signal with a highly accurate frequency. Generally, the video equipment, such as a set-top terminal, creates the video signal from its internally-generated clock. The accuracy of the internally-generated clock yields the accuracy of the timing contained or embedded in the video signal sent to a video display device, e.g., a television set or monitor. The timing needs to be accurate within a predetermine range for the image to be displayed properly. For example, the generation of images on the video display device, may require timing that is accurate to within 3 to 50 ppm. Some televisions require higher timing accuracy than others.
With television signals provided by network broadcasters, or cable or satellite companies, the required signal timing is inherently a part of an analog television signal and is always included as part of a digital television signal. Therefore, when a piece of video equipment takes control of a display device, e.g. a television set, and reconstructs an incoming video signal, the necessary clock signal with a sufficiently accurate frequency can be derived or borrowed from the incoming video signal.
In the past, video equipment requiring generation of a high-accuracy clock signal for supporting video reconstruction/generation has been provided with an internal clock circuit built around a dedicated crystal oscillator. The oscillator can either be calibrated at the factory to provide a sufficiently accurate clock signal to support video reconstruction/generation or designed and built with components having extremely tight tolerances. A voltage controlled crystal oscillator VCXO is a preferred oscillator for generating the necessary high-accuracy clock signal. Because the oscillator is voltage-controlled, it requires little or no factory calibration and can be continually controlled to adjust for the effects of initial accuracy, aging or extreme temperatures.
In this arrangement, the control voltage applied to the VCXO is measured and recorded when a video signal is being received and properly displayed. This is required for proper video construction and, in the digital channel case, for preventing buffer underruns and overruns. More particularly, the terminal has a recovered clock that is frequency locked to the encoder clock in the head-end or the location where the digital video signal was originally encoded. In the analog case, the terminal has a recovered clock that is locked to the timing embedded in an analog television signal. The clock frequency in currently-used applications is typically around 27 MHz.
To reconstruct an MPEG delivered video signal or an NTSC video signal, the frequency of the VCXO must be maintained at a sufficiently accurate frequency. This is a requirement for proper video construction in both analog and digital applications. Further, in digital applications, proper timing prevents buffer underruns and overruns as well. Usually, the VCXO is common to both MPEG decoding and NTSC video reconstruction and is designed to meet the MPEG specification on its allowable offset, manufacturing, and component tolerances with an additional margin. Typically, the allowable VCXO frequency range in this type of application is +/−100 ppm from the nominal 27 MHz value. Although this VCXO range is acceptable for decoding MPEG video signals, this range far exceeds the allowable range for regenerating NTSC video signals, resulting in color deterioration, the appearance of blocks in the image, frozen image portions, or degradation of the image into a black and white image. These image problems may also occur if the VCXO characteristics allows the frequency to drift beyond the allowable frequency range for decoding MPEG signals. Timing is also a concern in generating images from analog signals, where the VCXO needs to lock to the horizontal and/or vertical timing of an analog video signal.
Consequently, there is a need for a system that prevents the VCXO frequency from exceeding an allowable range for video reconstruction and buffer management.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus that outputs a clock signal for video reconstruction and that includes a control logic circuit with a phase locked loop for receiving an incoming video signal and phase locking to a clock signal portion of the incoming video signal, wherein the control logic circuit outputs a control signal for controlling an output of an oscillator, which serves as the clock signal, based on the phase lock, and a frequency range bounder in the phase locked loop that receives the control signal and outputs a bounded control signal that limits the frequency of the voltage controlled oscillator to a selected range.
The invention is also directed to a frequency range bounder apparatus for limiting an oscillator frequency range. The frequency range bounder receives a control signal for controlling an output of an oscillator and outputs either the control signal itself, if the control signal is within a selected range, or a threshold value, if the control signal is outside the selected range, as a bounded control signal to the oscillator to limit the oscillator frequency.
The invention is further directed to a method for outputting a clock signal for video reconstruction in a terminal, comprising the steps of receiving an incoming video signal in a control logic circuit with a phase locked loop, phase locking to a clock signal portion of the incoming video signal, outputting a control signal for controlling an output of an oscillator based on the phase lock, and limiting the frequency of the oscillator to a selected range using a frequency range bounder in the phase locked loop that receives the control signal.
As a result, the invention prevents the frequency of a voltage controlled oscillator from surpassing an allowable frequency range for proper video reconstruction as the oscillator locks to a head-end encoder's clock frequency or an analog video channel's embedded timing.
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Carroll Brian
Zeidler David E.
General Instrument Corporation
Kananen Ronald P.
Lee Michael H.
Nichols Steven L.
Rader Fishman and Grauer PLLC
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