Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-04-21
2002-12-24
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
C375S139000
Reexamination Certificate
active
06498822
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a frequency and timing synchronization circuit to be applied to a TDMA (Time Division Multiple Access) receiver making use of a chirp signal.
In a radio communication system such as a mobile communication system, where high-speed digital signals are transmitted through multi-paths changing their status every moment, it is very important for a receiver how to quickly and exactly establish initial synchronization of detection frequency and symbol timings with a receiving radio signal even in a low C/N (Carrier to Noise) ratio.
In a Japanese patent application entitled “Frequency Correction Apparatus” and laid open as a Provisional Publication No. H09-008765 (hereinafter called the first prior art), there is disclosed a method of correcting a reference frequency for detecting an OFDM (Orthogonal Frequency Division Multiplex) signal.
The frequency correction apparatus of the first prior art comprises a frequency converter having a controllable local oscillator for converting the OFDM radio-frequency signal into an intermediate-frequency signal, a quadrature demodulator for splitting the intermediate-frequency signal into an in-phase and a quadrature-phase signal, a complex FFT (Fast Fourier Transform) circuit for performing complex Fourier transformation of the in-phase and the quadrature-phase signal, and a power measurement circuit for obtaining a frequency distribution of power spectrums of the OFDM signal in a frequency domain from the output of the complex FFT circuit.
By detecting a center position of the frequency distribution when multi-carriers are arranged symmetrically to a center frequency of the OFDM signal in the frequency domain, or by detecting a position of a reference carrier when it is inserted in the OFDM signal with an intensity different to other carriers, the actual center frequency of the OFDM signal is determined and the local oscillator is feedback-controlled for acquiring frequency synchronization with the receiving signal, in the first prior art.
In another Japanese patent application entitled “A Frequency Error Detection Circuit by Detecting a Correlation Peak” and laid open as a Provisional Publication No. H09-200081 (hereinafter called the second prior art), a method of detecting a frequency error for controlling an AFC (Automatic Frequency Control) circuit is disclosed to be applied to a DSSS (Direct Sequence Spread Spectrum) receiver.
The frequency error detection circuit according to the second prior art comprises;
a first complex code generator for generating a first complex code which is obtained by giving a certain frequency offset to a pseudo random scramble code toward a positive side,
a second complex code generator for generating a second complex code obtained by giving the same frequency offset to the pseudo random scramble code toward a negative side,
a first and a second complex matched filter each calculating complex correlation of a base-band complex signal obtained through a quadrature demodulator with the first complex code and. the second complex code;
a peak timing detector for outputting a peak timing for every symbol where either or both of outputs of the first and the second complex matched filter show a maximum power value,
a first and a second peak average detector for outputting a first and a second peak average by calculating averages, for several symbols, of peak values which are extracted from outputs of the first and the second complex matched filter at each peak timing detected by the peak timing detector,
a first and a second power calculator for calculating power values of the first and the second peak average, respectively,
a power difference calculator for obtaining a normalized power difference by dividing a difference between outputs of the first and the second power calculator by a sum thereof, and
a frequency error converter for outputting a frequency error corresponding to the normalized power difference referring to a table memory.
The complex matched filter functions as a band-pass filter. Therefore, the power value of the first peak average becomes larger than that of the second peak average when a positive frequency error remains in the base-band complex signal, and vice versa, which is detected by the frequency error converter and converted into the frequency error to be fed back to the quadrature detector, in the frequency error detection circuit of the second prior art.
There is also a method of establishing frequency and timing synchronization making use of a chirp signal, which is to be applied to a mobile terminal, for example, receiving a SCH (Synchronization Channel) signal according to the TDMA communication system.
FIG. 3
is a block diagram illustrating a conventional frequency and timing synchronization circuit
104
making use of the chirp signal.
The frequency and timing synchronization circuit
104
of
FIG. 3
comprises a chirp signal generator
6
, a demodulator
7
and a detector unit
9
.
From a transmitter
1
, a radio signal, wherein certain symbols are scrambled with a chirp signal s(t) represented by following equation (1), is transmitted.
s
(
t
)
=
2
cos
(
π
t
2
μ
T
2
)
=
1
2
{
exp
(
j
π
t
2
μ
T
2
)
+
exp
(
-
j
π
t
2
μ
T
2
)
}
(
1
)
Here, t, &mgr; and T is a time counted from beginning of each symbol, a constant called a chirp rate, and a symbol cycle, respectively.
The radio signal arrives through transmission paths to a receiver added with a frequency shift &Dgr;f due to fading, for example, and therefore, the chirp signal r(t) in the received signal is expressed as follows.
r
(
t
)
=
s
(
t
)
·
exp
(
j2πΔ
f
t
)
=
1
2
{
exp
(
j
2
πΔ
f
t
+
j
π
t
2
μ
T
2
)
+
exp
(
j
2
πΔ
f
t
-
j
π
t
2
μ
T
2
)
}
(
2
)
The chirp signal generator
6
generates a reference chirp signal having the same chirp rate &mgr; with the transmission signal and expressed as
exp
(
j
π
(
t
+
Δ
t
)
2
μ
T
2
)
,
and its conjugate complex signal expressed as
exp
(
-
j
π
(
t
+
Δ
t
)
2
μ
T
2
)
,
&Dgr;t being a difference of symbol timings. The reference chirp signal and the conjugate complex signal are multiplied onto the received signal by the demodulator 7 for obtaining following two complex signals P(t) and Q(t) (hereinafter called the in-phase complex signal and the quadrature-phase complex signal, respectively) to analyzed by the detector unit
9
;
P
(
t
)
=
r
(
t
)
·
exp
(
j
π
(
t
+
Δ
t
)
2
μ
T
2
)
,
(
3
)
Q
(
t
)
=
r
(
t
)
·
exp
(
-
j
π
(
t
+
Δ
t
)
2
μ
T
2
)
.
(
4
)
FIG. 4
is a block diagram illustrating a configuration of the detector unit
9
of
FIG. 3
, comprising a complex FFT circuit
10
, a power detector
11
and a comparator
12
.
Each of the in-phase and the quadrature-phase complex signal P(t) and Q(t) is transformed into a frequency domain signal through the complex FFT circuit
10
, whereof a power value of each frequency component is calculated by the power detector
11
and a frequency component giving a maximum power spectrum is detected by the comparator
12
.
As to in-phase complex signal P(t) of equation (3), it is expressed as P(t)=A+B, where;
A
=
{
first
term
of
equation
Chin Stephen
Kim Kevin
NEC Corporation
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