Pulse or digital communications – Receivers – Amplitude modulation
Patent
1997-12-18
2000-02-15
Le, Amanda T.
Pulse or digital communications
Receivers
Amplitude modulation
375326, 375327, 375344, 375350, 348536, 348607, 348735, H04N 521
Patent
active
060261285
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a frequency and phase regulating circuit, particularly for a digital complex-value vestigial sideband signal or Nyquist flank-filtered signal.
BACKGROUND INFORMATION
In order to achieve a fixed-frequency and fixed-phase control system, it is described in IEEE Transactions on Communications, Vol. 37, No. 2, 1989,pages 159 to 163 to provide an additional AFC loop in addition to the narrow-band PLL loop. A quadricorrelator is suitable as a frequency error detector for the processing of digital signals.
A common frequency and phase regulation device, in which decimation occurs before the loop filter of the AFC loop and interpolation occurs afterward, is described in EP 583 643 A1. A quadricorrelator is also used therein as the frequency error detector.
SUMMARY OF THE INVENTION
The frequency and phase regulating circuit according to the present invention yields synchronization that is correct in frequency and phase, particularly for a digital complex-value vestigial sideband signal or a Nyquist flank-filtered signal.
The usual television signal (FBAS.sub.TT signal in modulated form) is a DSB (double sideband) signal with carrier, the lower sideband below f.sub.pc (picture carrier) minus 0.5 MHz being cut off and filtered out by means of a bandpass filter (anputated DSB signal, or ADSB). To demodulate a signal of this kind, mixing must occur in a frequency-correct and fixed-phase fashion in order to recover the modulated signal correctly.
The regulating circuit according to the invention ensures frequency slaving in a sufficient lock-in range. AFC thus and PLL jitter can be effectively suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of a TV demodulator having a regulating circuit according to the present invention.
FIG. 2 shows a block diagram for an embodiment of a regulating circuit according to the present invention.
FIG. 3 shows the structure of a low-pass filter to generate a symmetrical double sideband signal.
FIG. 4 shows the configuration of the frequency error detector.
FIG. 5 shows the spectrum components of the frequency error detector.
FIG. 6 shows further spectrum components of the frequency error detector.
FIG. 7 shows a simplified form of the frequency error detector.
FIG. 8 shows a quadricorrelator as a frequency error detector.
FIG. 9 shows the magnitude of the transfer function H.sub.PED.
FIG. 10 shows a block diagram for the frequency lock indicator.
FIG. 11 shows the transfer function of the prefilter and the spectrum of the VSB signal.
FIG. 12 shows the standardized frequency response of the prefilter for processing of a VSB signal.
FIG. 13 shows the structure of the prefilter as depicted in FIG. 12.
FIG. 14 shows a simplified model of the frequency regulating loop in the time range;
FIG. 15 shows a simplified model of the phase regulating loop, also in the time range.
FIG. 16 shows the structure of the PLL low-pass.
FIG. 17 shows the structure of the PLL low-pass in factored form.
FIG. 18 shows the structure of the PLL low-pass with decimation.
FIG. 19 shows a subfilter of the PLL in a recursive implementation.
DETAILED DESCRIPTION
The present invention is explained for the frequency and phase regulation of a digitized complex TV signal. However, those skilled in the art will understand that this is for exemplary purposes only and should not be interpreted as a limitation.
FIG. 1 shows a block diagram of a TV demodulator (without the audio portion), with a fixed-phase AFC/PLL frequency regulating system. The input-side FBAS.sub.TT signal in the IF position is conveyed to a preprocessing stage PP where it is prefiltered (anti-aliasing filter AAF), sampled (A/D) at a sampling frequency f.sub.S of, for example, 28.2763 MHz, optionally fed through a band filter RBF with real coefficients, and conveyed to a complex filter (vestigial sideband filter) CHBFT. The complex filter is preferably embodied as an L-band filter, with a decimation factor of, for example, L=2 (half-band filter). Further details of
REFERENCES:
patent: 5663773 (1997-09-01), Goeckler
patent: 5825833 (1998-10-01), Sakaue
T. Alberty et al., "A New Patter Jitter Free Frequency Error Detector", IEEE Transanctions On Communications, Feb. 19 vol. 37, No. 2, pp. 159-163.
Alberty Thomas
Goeckler Heinz
Le Amanda T.
Robert & Bosch GmbH
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