Frequency and phase offset signal generator and method

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

Reexamination Certificate

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Details

C331S025000, C331S027000, C331S018000, C327S106000, C327S107000

Reexamination Certificate

active

06278330

ABSTRACT:

TECHNICAL FIELD
The present invention relates to electric signal generation and more particularly to a signal generator and method of generation that can selectively offset frequency and phase by small increments.
BACKGROUND ART
Prior known signal generators provided output signals at a different frequency from the input frequency by dividing the input and output down to a common frequency with frequency dividers and comparing the resultant common frequency signals. The resolution of these signal generators is limited by the common frequency.
One signal generator that offsets frequency offsets phase by changing the frequency over a selected time interval has the disadvantage that the frequency and phase offsetting of this device is not independent and phase offsetting is not instantaneous.
Direct digital synthesizers have been used to phase shift signals. Japanese Patent Application/Public Disclosure Document No. 4-229703 shows a method of generating waveforms with a direct digital synthesizer (DDS). Ikuzawa, U.S. Pat. No. 5,517,156, shows a digital phase shifter using a DDS.
Look-up tables in memory have been used to phase shift signals. Takahashi, U.S. Pat. No. 5,732,109, and Treise et al., U.S. Pat. No. 4,484,296 show examples of waveform table look-up memories in variable phase generators and phase detectors. The use of look-up tables is limited in the resolution or increment size by the available memory for the tables.
DISCLOSURE OF THE INVENTION
A signal generator and method of signal generation is disclosed that provides independent offsetting of phase and frequency, instant phase and frequency offsetting, and a stable output signal. The signal generator includes first and second numerically controlled oscillators that sequentially divide down an input signal and phase and/or frequency offset this first divided down signal. The first divided down signal is upconverted to generate a reference signal. A third numerically controlled oscillator in a phase locked loop is clocked by the output signal of an output oscillator to divide down the output signal to generate a second divided down signal. The second divided down signal is upconverted to generate a control signal. The control signal and reference signal are mixed in a phase detector to control the output oscillator.


REFERENCES:
patent: 4484296 (1984-11-01), Treise et al.
patent: 5184092 (1993-02-01), Shahriary et al.
patent: 5451910 (1995-09-01), Gutherie
patent: 5517156 (1996-05-01), Ikuzawa
patent: 5732109 (1998-03-01), Takahashi
patent: 5841032 (1998-11-01), Froggatt
patent: 4-229703 (1992-08-01), None

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