Frequency and phase locked loop synthesizer

Details Frequency and phase locked loop synthesizer Frequency and phase locked loop synthesizer

2011-04-26

2011-04-26

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S011000

Reexamination Certificate

active

07932784

ABSTRACT:
The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. The FPLL synthesizer includes a variable frequency oscillator, which is controlled by FLL circuitry during the FLL operating mode or by PLL circuitry during the PLL operating mode. The FLL circuitry includes frequency division circuitry for reducing the frequency of the output signal, frequency detection circuitry for measuring the frequency error of the frequency reduced output signal, and a loop filter to control the bandwidth of an FLL control loop formed by the FLL circuitry and the variable frequency oscillator.

REFERENCES:
patent: 3538450 (1970-11-01), Andrea et al.
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 5446416 (1995-08-01), Lin et al.
patent: 5493715 (1996-02-01), Humphreys et al.
patent: 5631592 (1997-05-01), Schwarz et al.
patent: 6016080 (2000-01-01), Zuta et al.
patent: 6326961 (2001-12-01), Lin et al.
patent: 6710664 (2004-03-01), Humphreys et al.
patent: 7023282 (2006-04-01), Humpreys et al.
patent: 7064591 (2006-06-01), Humphreys et al.
patent: 7098754 (2006-08-01), Humphreys et al.
patent: 2004/0183601 (2004-09-01), Zhang
patent: 2005/0057290 (2005-03-01), Dalton et al.
patent: 2008/0231375 (2008-09-01), Welz et al.
Kral, A. et al., “RF-CMOS Oscillators with Switched Tuning,” IEEE 1998 Custom Integrated Circuits Conference, 1998, pp. 555-558, IEEE.
Wilson, William B., et al., “A CMOS Self-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, Oct. 10, 2000, pp. 1437-1444, vol. 35, No. 10, IEEE.
U.S. Appl. No. 11/082,277, now U.S. Patent No. 7,279,988, Notice of Allowance mailed May 31, 2007.
U.S. Appl. No. 11/082,277, now U.S. Patent No. 7,279,988, Final Rejection mailed Apr. 13, 2007.
U.S. Appl. No. 11/082,277, now U.S. Patent No. 7,279,988, Nonfinal Rejection mailed Nov. 3, 2006.
U.S. Appl. No. 12/251,757, now U.S. Patent No. 7,750,685, Notice of Allowance mailed Mar. 29, 2010.

Affiliated with

Also associated with

Rating

Frequency and phase locked loop synthesizer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Frequency and phase locked loop synthesizer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency and phase locked loop synthesizer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2633182