Frequency adjustment circuit

Details Frequency adjustment circuit Frequency adjustment circuit

2007-04-03

2007-04-03

Pascal, Robert (Department: 2817)

Oscillators

Relaxation oscillators

C331S111000, C331S135000, C331S137000, C331S150000, C331S17700V, C327S525000

Reexamination Certificate

active

11196512

ABSTRACT:
A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1and ZP2generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

REFERENCES:
patent: 4814640 (1989-03-01), Miyake
patent: 5450030 (1995-09-01), Shin et al.
patent: 2000-148064 (2000-05-01), None

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