Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2001-05-22
2004-09-21
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C375S376000, C327S156000, C331S017000
Reexamination Certificate
active
06794946
ABSTRACT:
BACKGROUND OF THE INVENTION
Monolithic data recovery phase locked loops (PLLs) require a large frequency capture range, due to the large frequency deviations of on-chip voltage-controlled oscillators (VCOs) caused by extensive process variations. As the capture range of a loop using only phase correction is limited, a frequency acquisition aid must be used.
One method that has been used is to directly measure the frequency of the VCO output, and when it is close to the target frequency, switch control of the VCO to the data recovery PLL. However, this requires extremely fast circuitry, especially at the high speeds (multi-gigabits per second) required in typical high-speed communication links.
SUMMARY OF THE INVENTION
The design employed by the present invention offers a new frequency acquisition technique which helps the main recovery PLL lock to data stream under considerable process variations.
Accordingly, a frequency monitor includes an edge detector which produces a pulse for each rising or falling edge of an error signal. The error signal itself has a frequency that is responsive to a difference between frequencies of two input signals. A resistive circuit has an effective average resistance that depends on the rate or frequency of the edge detector output pulses. A capacitor holds a charge that depends on the effective average resistance of the resistive circuit. Finally, an indicator circuit produces an output based on the charge held by the capacitor. The indicator circuit output indicates whether the difference between the two input signal frequencies is less than some predetermined amount.
The resistive circuit is implemented in one embodiment as a switched capacitor circuit that charges and discharges at a rate that depends on the rate of the edge detector output pulses.
The indicator circuit is implemented in one embodiment as a comparator that produces the indicator circuit output, which is at one of two levels based on the charge and some threshold, where one level indicating that the difference between the two input signal frequencies is less than a predetermined amount, and the second level indicating that said difference is greater than a predetermined amount.
Furthermore, a selector, responsive to the indicator circuit output, selects from plural sources, for example, a data phase detector circuit and a frequency acquisition circuit, to control an oscillator. The oscillator may be, for example, a voltage-controlled oscillator. It produces a clock signal at a sampling frequency, which is used by the detector circuit to receive data.
The frequency acquisition circuit compares the clock signal with a reference clock to produce a frequency acquisition output indicative of the difference between the frequencies of the reference clock and the oscillator clock signal. The output is one of the sources to the selector.
The data phase detector circuit compares the clock signal with a rate of incoming data to produce a data phase detector output indicative of the difference between the frequencies of the reference clock and the incoming data. The output another one of the sources to the selector.
In at least one embodiment, the data phase detector circuit output comprises the error signal.
In an alternate embodiment, the error signal is formed by a combiner circuit which combines the two input signals. For example, the combiner circuit can include a mixer which mixes the two input signals to produce a mixed signal, followed by a low-pass filter which filters the mixed signal to produce the error signal.
One advantage of the present invention is that the maximum frequency found in the present invention is equal to the difference between the frequencies of the input signal and the reference clock, which is considerably lower than the signal frequency. Thus, the acquisition loop can operate using standard CMOS technology.
Another advantage is that the frequency acquisition technique of the present invention can be used with any PLL regardless of its architecture. In other words, it is compatible with almost any PLL architecture.
Yet another advantage is that the existence of an input signal and frequency lock condition can be detected.
Finally, the overall architecture requires a very low transistor count and complexity.
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Soyuer, Mehmet, “A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology,” pp. 450-453, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-28, pp. 1310-1313, Dec. 1993.
Savoj, Jafar, et al., “A 10-Gb/s CMOS Clock and Data Recovery Circuit,” IEEE, pp. 136-139.
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Ishihara, Noboru, et al., “A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Same-and-Hold Technique,” pp. 431-436, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-29, pp. 1566-1571, Dec. 1994.
Farjad-Rad, Ramin, et al., “A 0.3-&mgr;m CMOS 8-Gb/s 4-PAM Serial Link Transceiver,” pp. 757-764, May 2000.
Fiedler, Alan, et al., “A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,” IEEE, pp. 462-464.
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Kinkead Arnold
Sawyer Law Group LLP
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