Frasable non-volatile semiconductor memory device having read/wr

Details Frasable non-volatile semiconductor memory device having read/wr Frasable non-volatile semiconductor memory device having read/wr

1991-11-20

1993-08-17

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365201, G11C 2900

Patent

active

052375307

ABSTRACT:
An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the "0" data and "1" data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.

REFERENCES:
patent: 4651304 (1987-03-01), Takata
patent: 4870618 (1989-09-01), Iwashita
patent: 4956819 (1990-09-01), Hoffmann et al.
patent: 5124945 (1992-06-01), Schreck

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