Framing timing detection circuit for a character code broadcasti

Details Framing timing detection circuit for a character code broadcasti Framing timing detection circuit for a character code broadcasti

1986-08-08

1989-04-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370100, H04J 326

Patent

active

048192317

ABSTRACT:
A random multi-error correcting code having a maximum length block in a packet, for instance a majority logic decodable (272, 190) shortened difference set cyclic code, is used for error correction in a character code broadcasting system. The error correcting ability of this code is increased. The correction is made by decreasing a threshold value, so that the error correcting ability is improved. A framing timing extraction circuit and a phase lock circuit for the framing timing are eliminated, so that the amount of hardware needed is reduced. Preferably, the error correcting code is superposed on the television signal during the vertical blanking period.

REFERENCES:
patent: 4203070 (1980-05-01), Bowles et al.
patent: 4590601 (1986-05-01), Beeman

Affiliated with

Also associated with

Rating

Framing timing detection circuit for a character code broadcasti does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Framing timing detection circuit for a character code broadcasti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Framing timing detection circuit for a character code broadcasti will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-185769