Framing circuit that increases the pulse width of the byte clock

Details Framing circuit that increases the pulse width of the byte clock Framing circuit that increases the pulse width of the byte clock

1996-02-28

1996-11-12

Kriess, Kevin A.

Pulse or digital communications

Repeaters

Testing

375368, 377 75, 3649395, 3649261, 3649265, 364DIG2, H04L 700

Patent

active

055748961

ABSTRACT:
A framing circuit, which frames bytes of data received from a serial data bit stream, prevents a short byte clock pulse from being formed when the byte clock signal, which identifies the beginning of each frame, is reset. The framing circuit utilizes a comparison stage to output a match signal each time an n-bit data bit pattern matches a programmable predetermined framing pattern, and to delay each n-bit pattern a delay time. The framing circuit also utilizes a counter to produce the byte clock signal, and a delay circuit to freeze the output of the counter for a predetermined delay time each time the match signal is output. The delay circuit also resets the byte clock signal so that the reset byte clock signal coincides with the output of the delayed data bit pattern. By freezing the output of the counter for a predetermined time, the width of the resulting pulse is lengthened.

REFERENCES:
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patent: 4605921 (1986-08-01), Riddle et al.
patent: 4765652 (1987-06-01), Machado
patent: 4835768 (1989-05-01), Hubbard et al.
patent: 4885583 (1989-12-01), McCambridge
patent: 5081654 (1992-01-01), Stephenson et al.
patent: 5289439 (1994-02-01), Koulopoulos et al.
National Semiconductor Fiber Distributed Data Interface (FDDI) Databook, 1994, pp. (1-39)-(1-41).
Preliminary Data Sheet: Am79865/Am79866 Physical Data Transmitter/Physical Data Receiver, Advanced Micro Devices.

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